Backside illumination type solid-state imaging device, manufacturing method for backside illumination type solid-state imaging device, imaging apparatus and electronic equipment

ABSTRACT

The present disclosure relates to a backside illumination type solid-state imaging device, a manufacturing method for a backside illumination type solid-state imaging device, an imaging apparatus, and electronic equipment by which the manufacturing cost can be reduced. A singulated memory circuit and a singulated logic circuit are laid out in a horizontal direction and are embedded by an oxide film and flattened, and then are stacked so as to be contained in a plane direction under a solid-state imaging element. The present disclosure can be applied to an imaging apparatus.

TECHNICAL FIELD

The present disclosure relates to a backside illumination typesolid-state imaging device, a manufacturing method for a backsideillumination type solid-state imaging device, an imaging apparatus andelectronic equipment, and particularly to a backside illumination typesolid-state imaging device, a manufacturing method for a backsideillumination type solid-state imaging device, an imaging apparatus andelectronic equipment by which the manufacturing cost can be reduced.

BACKGROUND ART

A solid-state imaging device achieves high picture quality in the formof Hi-Vision, 4 k×2 k Super Hi-Vision and a super slow-motion function,and together with this, the number of pixels increases and a high framerate and a high gradation are attained.

Since the transmission rate is calculated by the number of pixels×framerate×gradation, for example, in the case of 4 k×2 k=8M pixels, a framerate of 240 f/s and a gradation of 14 bits, the transmission rate is8M×240 f/s×14 bits=26 Gbps.

After signal processing by the succeeding stage of a solid-state imagingelement, RGB signals of a color coordinate are outputted, and therefore,higher-speed transmission of 26G×3=78 Gbps is required.

If high-speed transmission is performed with a reduced number ofconnection terminals, then the signal rate per one connection terminalbecomes high and the difficulty for impedance matching of a high-speedtransmission path increases. Further, since not only the clock frequencybut also the loss increases, power consumption increases.

In order to avoid this, it is sufficient if the number of connectionterminals is increased such that transmission is divided to decrease thesignal rate. However, increase of the number of connection terminalsincreases the package size of individual circuits because terminalsnecessary for connection between a solid-state imaging element and asignal processing circuit or a memory circuit on the following stage arearranged.

Also, as a substrate for electric wiring necessary for a signalprocessing circuit or a memory circuit on the succeeding stage, asubstrate having a finer wire density based on stacked wiring isrequired, and this further increases the wiring path length. Togetherwith this, the power consumption increases.

If the package size of individual circuits becomes great, then also thesize of a substrate itself for mounting becomes great, and the imagingapparatus configuration itself in which the solid-state imaging elementis to be incorporated finally becomes great.

Therefore, as a technology for downsizing the configuration of animaging apparatus, a technology is proposed by which a solid-stateimaging element and a circuit such as a signal processing circuit or amemory circuit are stacked by WoW (Wafer on Wafer) for connecting thecircuits both in the form of a wafer (refer to PTL 1).

Since, by a stacking technology using the WoW, a semiconductor can beconnected by many fine wires, the transmission speed per one wirebecomes low and the power consumption can be suppressed.

CITATION LIST Patent Literature

-   [PTL 1]-   Japanese Patent Laid-Open No. 2014-099582

SUMMARY Technical Problem

However, in the case of the WoW, if chips of wafers to be stacked have asame size, there is no problem. However, if the sizes of the chipsconfigured as wafers are different from each other, then the sizes mustbe adjusted to that of the greatest chip, and the theoretical yield foreach circuit is degraded and the cost increases.

Further, in regard to the yield of each of wafers to be stacked, by adefect of a chip of each wafer, also a chip of the stacked wafers istreated as a defect, and since the yield of the wafers in the entirestacked layers is given by the product (cross) of the yields of thewafers, the yield is degraded and the cost increases.

Also, a technology has been proposed by which chips whose sizes aredifferent from each other are connected to each other by forming smallbumps on them. In this case, since chips selected as good products andhaving different sizes are connected through the bumps, the influence ofthe theoretical yield difference between the wafers and the yield of thechips is small.

However, since it is difficult to form small bumps and the connectionpitch is limited, a greater number of connection terminals than that bythe WoW cannot be obtained. Further, since the connection is performedby a mounting process, if the number of connection terminals increases,then the cost increases due to yield degradation by the connection.Further, since also connection in the mounting process is performed forindividual wires, long time is required for the connection and theprocess cost increases.

The present disclosure has been made in view of such a situation asdescribed above and specifically makes it possible to reduce themanufacturing cost of a solid-state imaging device.

Solution to Problem

A solid-state imaging element of one aspect of the present disclosure isa backside illumination type solid-state imaging device including: afirst semiconductor element including an imaging element configured togenerate a pixel signal in a unit of a pixel; a second semiconductorelement in which signal processing circuits necessary for signalprocessing of the pixel signal are embedded by an embedding member; anda wire that electrically connects the first semiconductor element andthe second semiconductor element; the first semiconductor element andthe second semiconductor element being stacked by oxide film joining.

The first semiconductor element may be greater than the secondsemiconductor element.

The first semiconductor element may smaller than the secondsemiconductor element.

The backside illumination type solid-state imaging device may beconfigured such that the signal processing circuits include a firstsignal processing circuit and a second signal processing circuit, andthe second semiconductor element has therein the first signal processingcircuit and the second signal processing circuit arranged in ajuxtaposed relation in a horizontal direction and embedded by theembedding member.

The backside illumination type solid-state imaging device may beconfigured such that the signal processing circuits include a firstsignal processing circuit and a second signal processing circuit, thewire includes a first wire and a second wire, the second semiconductorelement has therein the first signal processing circuit embedded by theembedding member, the solid-state imaging device includes a thirdsemiconductor element in which the second signal processing circuit isembedded by the embedding member, the first wire electrically connectsthe first semiconductor element and the second semiconductor element toeach other, the second wire electrically connects the secondsemiconductor element and the third semiconductor element to each other,and the second semiconductor element and the third semiconductor elementare stacked by oxide film joining.

The wire may be joined by CuCu joining.

The wire may electrically connect the first semiconductor element andthe second semiconductor element through a through-via.

The wire may electrically connect the first semiconductor element andthe second semiconductor element through a through-via formed from animaging face side of the imaging element.

The wire may electrically connect the first semiconductor element andthe second semiconductor element through a through-via formed from aface on an opposite side to an imaging face of the imaging element.

The embedding member may include an oxide film.

The embedding member may include an organic material.

The backside illumination type solid-state imaging device may beconfigured such that, in the second semiconductor element, the signalprocessing circuits are laid out such that a gap between the signalprocessing circuits is minimized, and the gap is filled with theembedding member including the organic material.

In the second semiconductor element, in addition to the signalprocessing circuits, a dummy circuit configured from a semiconductorelement and including a dummy wire may be embedded by the embeddingmember.

A heat dissipation member that includes a member having a thermalconductivity higher than a predetermined thermal conductivity anddissipates heat may be stacked on a face of the second semiconductorelement opposite to a face on which the first semiconductor element isstacked.

The heat dissipation member may include SiC, AlN, SIN, Cu, Al, and C.

The heat dissipation member may include a waterway for circulatingcooling water.

The signal processing circuits may include a logic circuit, a memorycircuit, a power supply circuit, an image signal compression circuit, aclock circuit, and an optical communication conversion circuit.

The signal processing circuits may be embedded in the firstsemiconductor element by the embedding member.

The signal processing circuits may be each embedded by the embeddingmember after contacted at part thereof in a positioned state with thefirst semiconductor element and gradually joined to the firstsemiconductor element beginning with a portion around the contactedportion.

The part may include an end side and an end point of the signalprocessing circuit.

The signal processing circuit may be smaller than the firstsemiconductor element.

The signal processing circuits may be each embedded by the embeddingmember after contacted at part thereof in a positioned state with thesecond semiconductor element and gradually joined to the secondsemiconductor element beginning with a portion around the contactedportion.

The part may include an end side and an end point of the signalprocessing circuit.

A manufacturing method for a solid-state imaging device of one aspect ofthe present disclosure is a manufacturing method for a backsideillumination type solid-state imaging device that includes a firstsemiconductor element including an imaging element configured togenerate a pixel signal in a unit of a pixel, a second semiconductorelement in which signal processing circuits necessary for signalprocessing of the pixel signal are embedded by an embedding member, anda wire that electrically connects the first semiconductor element andthe second semiconductor element, the first semiconductor element andthe second semiconductor element being stacked by oxide film joining. Afirst wafer including the imaging element formed by a semiconductorprocess and a second wafer in which the signal processing circuitdecided as a good product by electric inspection from among the signalprocessing circuits formed by a semiconductor process is rearranged andembedded by the embedding member are stacked by oxide film joining suchthat the wire between the first semiconductor element and the secondsemiconductor element is electrically connected and then are singulated.

An imaging apparatus of one aspect of the present disclosure is animaging apparatus including a backside illumination type solid-stateimaging device that includes a first semiconductor element including animaging element configured to generate a pixel signal in a unit of apixel, a second semiconductor element in which signal processingcircuits necessary for signal processing of the pixel signal areembedded by an embedding member, and a wire that electrically connectsthe first semiconductor element and the second semiconductor element,the first semiconductor element and the second semiconductor elementbeing stacked by oxide film joining.

Electronic equipment of one aspect of the present disclosure iselectronic equipment including a backside illumination type solid-stateimaging device that includes a first semiconductor element including animaging element configured to generate a pixel signal in a unit of apixel, a second semiconductor element in which signal processingcircuits necessary for signal processing of the pixel signal areembedded by an embedding member, and a wire that electrically connectsthe first semiconductor element and the second semiconductor element,the first semiconductor element and the second semiconductor elementbeing stacked by oxide film joining.

According to one aspect of the present disclosure, the firstsemiconductor element including the imaging element configured togenerate a pixel signal in a unit of a pixel and the secondsemiconductor device in which signal processing circuits necessary forsignal processing of the pixel signal are embedded by the embeddingmember are electrically connected by the wire, and the firstsemiconductor element and the second semiconductor element are stackedby oxide film joining.

Advantageous Effect of the Invention

According to one aspect of the present disclosure, the manufacturingcost especially of the solid-state imaging device can be decreased.

BRIEF DESCRIPTION OF DRAWINGS

FIG. 1 is a view illustrating the yield.

FIG. 2 is a view illustrating reduction of the theoretical yield.

FIG. 3 is a view illustrating connection using a bump.

FIG. 4 is a view illustrating an overview of a manufacturing method fora solid-state imaging device of a first embodiment of the presentdisclosure.

FIG. 5 is a view illustrating an example of a configuration of thesolid-state imaging device of the first embodiment of the presentdisclosure.

FIG. 6 is a view illustrating the manufacturing method for a solid-stateimaging device of FIG. 5.

FIG. 7 is a view illustrating the manufacturing method for a solid-stateimaging device of FIG. 5.

FIG. 8 is a view illustrating the manufacturing method for a solid-stateimaging device of FIG. 5.

FIG. 9 is a view illustrating the manufacturing method for a solid-stateimaging device of FIG. 5.

FIG. 10 is a view illustrating an overview of a manufacturing method fora solid-state imaging device of a second embodiment of the presentdisclosure.

FIG. 11 is a view illustrating an example of a configuration of asolid-state imaging device of the second embodiment of the presentdisclosure.

FIG. 12 is a view illustrating the manufacturing method for asolid-state imaging device of FIG. 10.

FIG. 13 is a view illustrating the manufacturing method for asolid-state imaging device of FIG. 10.

FIG. 14 is a view illustrating an example of a configuration of asolid-state imaging device of a third embodiment of the presentdisclosure.

FIG. 15 is a view illustrating the manufacturing method for thesolid-state imaging device of FIG. 14.

FIG. 16 is a view illustrating the manufacturing method for thesolid-state imaging device of FIG. 14.

FIG. 17 is a view illustrating an example of a configuration of asolid-state imaging device of a fourth embodiment of the presentdisclosure.

FIG. 18 is a view illustrating an example of a configuration of asolid-state imaging device of a fifth embodiment of the presentdisclosure.

FIG. 19 is a view illustrating a manufacturing method of the solid-stateimaging device of FIG. 18.

FIG. 20 is a view illustrating the manufacturing method of thesolid-state imaging device of FIG. 18.

FIG. 21 is a view illustrating the manufacturing method of thesolid-state imaging device of FIG. 18.

FIG. 22 is a view illustrating the manufacturing method of thesolid-state imaging device of FIG. 18.

FIG. 23 is a view illustrating an example of a configuration of asolid-state imaging device that is a modification of the fifthembodiment of the present disclosure.

FIG. 24 is a view illustrating an overview of a manufacturing method ofa solid-state imaging device of a sixth embodiment of the presentdisclosure.

FIG. 25 is a view illustrating an example of a configuration of asolid-state imaging device of a sixth embodiment of the presentdisclosure.

FIG. 26 is a view illustrating a manufacturing method of the solid-stateimaging device of FIG. 25.

FIG. 27 is a view illustrating the manufacturing method of thesolid-state imaging device of FIG. 25.

FIG. 28 is a view illustrating the manufacturing method of thesolid-state imaging device of FIG. 25.

FIG. 29 is a view illustrating a first connection example to thesolid-state imaging element.

FIG. 30 is a view illustrating a manufacturing method of the solid-stateimaging device of FIG. 29.

FIG. 31 is a view illustrating the manufacturing method of thesolid-state imaging device of FIG. 29.

FIG. 32 is a view illustrating the manufacturing method of thesolid-state imaging device of FIG. 29.

FIG. 33 is a view illustrating a second connection example to thesolid-state imaging element.

FIG. 34 is a view illustrating a manufacturing method of the solid-stateimaging device of FIG. 33.

FIG. 35 is a view illustrating the manufacturing method of thesolid-state imaging device of FIG. 33.

FIG. 36 is a view illustrating the manufacturing method of thesolid-state imaging device of FIG. 33.

FIG. 37 is a view illustrating a first modification of the connectionexample to the solid-state imaging element.

FIG. 38 is a view illustrating a second modification of the connectionexample to the solid-state imaging element.

FIG. 39 is a view illustrating a third modification of the connectionexample to the solid-state imaging element.

FIG. 40 is a view illustrating a fourth modification of the connectionexample to the solid-state imaging element.

FIG. 41 is a view illustrating a fifth modification of the connectionexample to the solid-state imaging element.

FIG. 42 is a view illustrating a sixth modification of the connectionexample to the solid-state imaging element.

FIG. 43 is a view illustrating a heat dissipation structure of thesolid-state imaging device.

FIG. 44 is a view illustrating a manufacturing method of the solid-stateimaging device.

FIG. 45 is a view illustrating a first modification of the heatdissipation structure of the solid-state imaging device.

FIG. 46 is a view illustrating a second modification of the heatdissipation structure of the solid-state imaging device.

FIG. 47 is a view illustrating a third modification of the heatdissipation structure of the solid-state imaging device.

FIG. 48 is a view illustrating a fourth modification of the heatdissipation structure of the solid-state imaging device.

FIG. 49 is a block diagram depicting an example of a configuration of animaging apparatus as electronic equipment to which the configuration ofthe imaging apparatus of the present disclosure is applied.

FIG. 50 is a view illustrating an example of use of the imagingapparatus to which the technology of the present disclosure is applied.

FIG. 51 is a view depicting an example of a schematic configuration ofan endoscopic surgery system.

FIG. 52 is a block diagram depicting an example of a functionalconfiguration of a camera head and a camera control unit (CCU).

FIG. 53 is a block diagram depicting an example of schematicconfiguration of a vehicle control system.

FIG. 54 is a diagram of assistance in explaining an example ofinstallation positions of an outside-vehicle information detectingsection and an imaging section.

DESCRIPTION OF EMBODIMENTS

In the following, a mode for carrying out the present disclosure isdescribed. It is to be noted that, in the present specification and thedrawings, components having substantially same functional configurationsare denoted by same reference signs, and overlapping description of themis omitted.

The description is given in the following order.

1. Overview of the Present Disclosure

2. First Embodiment

3. Second Embodiment

4. Third Embodiment

5. Fourth Embodiment

6. Fifth Embodiment

7. Modification of Fifth Embodiment

8. Sixth Embodiment

9. Example of Connection to Solid-State Imaging Element

10. Modification of Example of Connection to Solid-State Imaging Element

11. Heat Dissipation Structure

12. Example of Application to Electronic Equipment

13. Example of Use of Imaging Element

14. Example of Application to Endoscopic Surgery System

15. Example of Application to Mobile Body

1. Overview of the Present Disclosure

The present disclosure reduces the manufacturing cost of a solid-stateimaging device.

Here, before the present disclosure is described, the WoW (Wafer onWafer) disclosed in PTL 1 is described.

The WoW is a technology for joining and stacking a solid-state imagingdevice, a signal processing circuit, and circuits including ICs such asmemory circuits each in the form of wafer, for example, as depicted inFIG. 1.

FIG. 1 schematically represents a WoW in which a wafer W1 on which aplurality of solid-state imaging elements 11 is formed, a wafer W2 onwhich a plurality of memory circuits 12 is formed, and a wafer W3 onwhich a plurality of logic circuits 13 is formed are joined to andstacked on each other in a state in which they are positioned accuratelyrelative to each other.

By singulating the wafers stacked in this manner, such a solid-stateimaging device as depicted, for example, in FIG. 2 is formed.

The solid-state imaging device 1 of FIG. 2 is configured such that anon-chip lens and on-chip color filter 10, a solid-state imaging element11, a memory circuit 12, a logic circuit 13 and a support substrate 14are stacked in this order from above.

Here, by applying the technology of the WoW, wires 21-1 for electricallyconnecting the solid-state imaging element 11 and the memory circuit 12and wires 21-2 for electrically connecting the memory circuit 12 and thelogic circuit 13 can be connected at a fine pitch.

As a result, since the number of wires can be increased, thetransmission speed in signal lines can be reduced and power saving canbe anticipated.

However, since the areas necessitated for the solid-state imagingelement 11, memory circuit 12 and logic circuit 13 to be stacked aredifferent from one another, a space Z1 in which neither circuit nor wireare formed appears on the left and right in the figure of the memorycircuit 12 that has an area smaller than that of the solid-state imagingelement 11 that is greatest. Further, on the left and right of the logiccircuit that has an area smaller than that of the memory circuit 12, aspace Z2 in which neither circuit nor wire are formed appears.

In particular, the spaces Z1 and Z2 appear arising from that the areasnecessitated by the solid-state imaging element 11, memory circuit 12and logic circuit 13 are different from one another and, in FIG. 2,arising from that the they are stacked with reference to the solid-stateimaging element 11 for which the largest area is necessitated.

This decreases the theoretical yield relating to manufacture of thesolid-state imaging device 1 and, as a result, increases the costrequired for manufacture.

Further, in FIG. 1, elements that are defective in the solid-stateimaging element 11, the memory circuit 12, and the logic circuit 13formed on the wafers W1 to W3, respectively, are individuallyrepresented by filled cells. In particular, FIG. 1 depicts that twodefective elements appear in each of the wafers W1 to W3.

As depicted in FIG. 1, the defective elements appearing in thesolid-state imaging element 11, the memory circuit 12, and the logiccircuit 13 formed on the wafers W1 to W3, respectively, are notnecessarily formed at same positions. Therefore, as depicted in FIG. 1,in the solid-state imaging device 1 formed from the stack suffer fromsix defectives each indicated by a cross mark applied to the wafer W1 ofthe solid-state imaging element 11.

Consequently, in the six defective solid-state imaging devices 1,although at least two parts from among the three parts of thesolid-state imaging element 11, memory circuit 12 and logic circuit 13are not defective, they are treated as six defectives. Thus, although itis sufficient if the yield in regard to each part is two, the yield inregard to each part becomes six that is equal to an integrated number bythe number of wafers.

As a result, the yield of the solid-state imaging devices 1 is decreasedand the manufacturing cost is increased.

Further, as depicted in FIG. 3, it is conceivable to singulatesolid-state imaging elements 11, memory circuits 12 and logic circuits13 having chip sizes different from each other, selectively arrange onlygood products and form small bumps to connect them.

In the solid-state imaging device 1 of FIG. 3, an on-chip lens andon-chip color filter 10 and a solid-state imaging element 11 are stackedfrom above, and below them, a memory circuit 12 and a logic circuit 13are stacked in a same layer, under which a support substrate 14 isprovided and stacked. Further, the solid-state imaging element 11 andthe memory circuit 12 and logic circuit 13 that are arranged in the samelayer are electrically connected to each other through small-sized bumps31.

In the solid-state imaging device 1 of FIG. 3, chips of sizes selectedas good products are connected through the bumps 31 and the theoreticalyield difference between the wafers and the influence of the yields thechips are reduced.

However, formation of the small-sized bumps 31 is difficult, and sincethere is a limitation to decrease of the connection pitches d2 asdepicted in FIG. 3, the connection pitches d2 cannot be made smallerthan the connection pitches d1 of FIG. 2 in the case where the WoW isused.

Therefore, the solid-state imaging device 1 of FIG. 3 in which the chipsare stacked using bumps cannot have a great number of connectionterminals in comparison with the solid-state imaging device 1 of FIG. 2stacked by the WoW. Further, in the case of the connection that usesbumps like the solid-state imaging device 1 of FIG. 3, if the connectionterminal number increases, then since the connection terminals arejoined by a mounting process, reduction of the yield relating to joiningoccurs and increases the cost. Further, since the connection of thebumps in the mounting process is performed by individual works, eachprocess requires long time and also the process cost increases.

From the foregoing, the imaging element of the present disclosuredecreases the cost for manufacture in terms of the theoretical yield,implementation cost and process cost.

2. First Embodiment

FIG. 4 is a view illustrating a structure in which a plurality of wafersis stacked by the WoW technology that is applied when the solid-stateimaging device of the present disclosure is to be manufactured.

In manufacturing the solid-state imaging device of the presentdisclosure, two wafers including a wafer 101 on which a plurality ofsolid-state imaging element (CMOS (Complementary Metal OxideSemiconductor)) image sensors and CCDs (Charge Coupled Devices) 120 areformed and a wafer 102 on which memory circuits 121 and logic circuits122 are rearranged are stacked in a state in which wires are positionedaccurately relative to each other.

The wafer 101 has a plurality of solid-state imaging elements 120 formedthereon by a semiconductor process.

The wafer 102 has rearranged thereon a plurality of memory circuits 121that has been subjected, after the memory circuits 121 have been formedon a wafer 103 by a semiconductor process and singulated, to electricinspection individually and has been confirmed as good chips through theelectric inspection.

The wafer 102 has rearranged thereon a plurality of logic circuits 122that has been subjected, after the logic circuits 122 have been formedon a wafer 104 by a semiconductor process and singulated, to electricinspection individually and has been confirmed as good chips through theelectric inspection.

<Example of configuration of solid-state imaging device including wafersstacked by WoW technology of FIG. 4>

After a plurality of wafers is stacked by such a WoW technology asdepicted in FIG. 4, the wafers are singulated to configure a solid-stateimaging device 111 (FIG. 5) of the present disclosure.

The solid-state imaging device of the present disclosure has such aconfiguration, for example, as depicted in FIG. 5. It is to be notedthat, in FIG. 5, an upper stage is a side elevational sectional view anda lower stage is a view illustrating an arrangement relation in ahorizontal direction when the solid-state imaging element 120, memorycircuit 121 and logic circuit 122 are viewed from above.

In the solid-state imaging device 111 at the upper stage of FIG. 5, anon-chip lens and on-chip color filter 131 and a solid-state imagingelement 120 are stacked from above in the figure, and below them, amemory circuit 121 and a logic circuit 122 are arranged left and rightand stacked in a same layer, below which a support substrate 132 isformed. In other words, as depicted by the upper stage of FIG. 5, thesolid-state imaging device 111 of FIG. 5 has: a semiconductor deviceelement E1 including the solid-state imaging element 120 including thewafer 101; and a semiconductor element layer E2 formed on the wafer 102and including the memory circuit 121 and the logic circuit 122.

Of terminals 120 a of the solid-state imaging element 120, the terminals120 a on the memory circuit 121 are electrically connected to wires 134connected by CuCu connection to terminals 121 a of the memory circuit121.

Further, of the terminals 120 a of the solid-state imaging element 120,the terminals 120 a on the logic circuit 122 are electrically connectedto wires 134 connected to terminals 122 a of the logic circuit 122 byCuCu connection.

A space around the memory circuit 121 and the logic circuit 122 in thesemiconductor element layer E2 in which memory circuit 121 and the logiccircuit 122 are formed is in a state in which it is filled with an oxidefilm 133. Consequently, in the semiconductor element layer E2, thememory circuit 121 and the logic circuit 122 are in a state in whichthey are embedded in the oxide film 133. Further, on the boundarybetween the semiconductor element layer E1 in which the solid-stateimaging element 120 is formed and the semiconductor element layer E2 inwhich the memory circuit 121 and the logic circuit 122 are formed, anoxide film joining layer 135 is formed and joins them together by oxidefilm joining. Furthermore, the semiconductor element layer E2 of thememory circuit 121 and the logic circuit 122 and the support substrate132 are joined together by an oxide film joining layer 135 formedbetween them by oxide film joining.

Further, as depicted at the lower stage of FIG. 5, the memory circuit121 and the logic circuit 122 are arranged such that they are includedin a range in which the solid-state imaging element 120 of the uppermostlayer is contained as viewed from above. By such arrangement, in thelayer of the memory circuit 121 and the logic circuit 122, the freespace other than the memory circuit 121 and the logic circuit 122 isreduced, and therefore, theoretical yield can be improved.

On the wafer 102 of FIG. 4, when each solid-state imaging device 111 issingulated, the memory circuit 121 and the logic circuit 122 arerearranged in an elaborately adjusted state such that they are arrangedin a range of the solid-state imaging element 120 as viewed from above.

<Manufacturing method of solid-state imaging device of FIG. 5>

Now, a manufacturing method of the solid-state imaging device 111 ofFIG. 5 is described with reference to FIGS. 6 to 9. It is to be notedthat side elevational sectional views 6A to 6L of FIGS. 6 to 9 depictside elevational sectional views of the solid-state imaging device 111.

At a first step, as depicted by the side elevational sectional view 6Aof FIG. 6, after electric inspection is performed, a memory circuit 121and a logic circuit 122 that have been confirmed as good products arerearranged on a rearrangement substrate 151 such that they have such alayout as depicted at the lower stage of FIG. 5. On the rearrangementsubstrate 151, adhesive 152 is applied, and the memory circuit 121 andthe logic circuit 122 are rearranged on and fixed to the rearrangementsubstrate 151 by the adhesive 152.

At a second step, as depicted by the side elevational sectional view 6Bof FIG. 6, the memory circuit 121 and the logic circuit 122 depicted inthe side elevational sectional view 6A are reversed such that the upperface thereof becomes a lower face, and an oxide film joining layer 135is formed on a support substrate 161 flattened by an oxide film formedthereon and is joined by oxide film joining.

At a third step, the rearrangement substrate 151 is debonded,exfoliated, and removed together with the adhesive 152 as depicted inthe side elevational sectional view 6C of FIG. 6.

At a fourth step, as depicted in the side elevational sectional view 6Dof FIG. 7, the silicon layer at the upper face portion in the figure ofthe memory circuit 121 and the logic circuit 122 is thinned to such aheight H that does not have an influence on a property of the devices.

At a fifth step, as depicted by the side elevational sectional view 6Eof FIG. 7, an oxide film 133 that functions as an insulating film isformed to embed the chip including the rearranged memory circuit 121 andlogic circuit 122. At this time, the face of the oxide film 133 isflattened at a height corresponding to the memory circuit 121 and thelogic circuit 122.

At a sixth step, as depicted by the side elevational sectional view ofFIG. 6F of FIG. 7, an oxide film joining layer 135 is formed on theflattened oxide film 133 and a support substrate 171 is joined to theoxide film 133 by oxide film joining.

At a seventh step, as depicted by the side elevational sectional view 6Gof FIG. 8, the support substrate 171 is removed by debonding or etching.By the processes from the first step to the seventh step, the wafer 102is placed into a completed state in which the memory circuit 121 and thelogic circuit 122 are rearranged in the layout depicted at the lowerstage of FIG. 5 and filled with the insulating film including the oxidefilm 133 and has the oxide film joining layer 135 formed on theflattened uppermost face.

At an eighth step, as depicted by the side elevational sectional view 6Hof FIG. 8, wires 134 are formed for terminals 121 a of the memorycircuit 121 and terminals 122 a of the logic circuit 122 forelectrically connecting to the solid-state imaging element 120.

At a ninth step, as depicted by the side elevational sectional view 6Iof FIG. 8, positioning is performed such that the wires 134 from theterminals 121 a of the memory circuit 121 and the terminals 122 a of thelogic circuit 122 of the wafer 102 and the wires 134 from the terminals120 a of the solid-state imaging element 120 of the wafer 101 arepositioned in an appropriately opposing relation to each other.

At a tenth step, as depicted by the side elevational sectional view 6Jof FIG. 9, the wafers 101 and 102 are pasted to each other by the WoWsuch that the wires 134 from the terminals 121 a of the memory circuit121 and the terminals 122 a of the logic circuit 122 of the wafer 102and the wires 134 from the terminals 120 a of the solid-state imagingelement 120 of the wafer 101 are connected by CuCu joining. By thisprocess, the memory circuits 121 and the logic circuits 122 of the wafer102 are placed into an electrically connected state to the individualsolid-state imaging elements 120 of the wafer 101.

At an eleventh step, as depicted by the side elevational sectional view6K of FIG. 9, the silicon layer that is an upper layer in the figure ofthe solid-state imaging element 120 is thinned.

At a twelfth step, as depicted by the side elevational sectional view 6Lof FIG. 9, an on-chip lens and on-chip color filter 131 is provided onthe solid-state imaging element 120 and singulation is performed to formthe solid-state imaging device 111.

By such steps as described above, the solid-state imaging device 111including the first layer on which the solid-state imaging element 120is formed and the second layer on which the memory circuit 121 and thelogic circuit 122 are formed is manufactured.

By such configuration as described above, since circuit connectionbetween the solid-state imaging element 120 and the memory circuit 121and the logic circuit 122 can be established through terminals formed ina wire density of fine wires by a lithography technique ofsemiconductors similarly as in the WoW, the number of connectionterminals can be increased and the signal processing speed by each wirecan be reduced. Therefore, reduction of the power consumption can beanticipated.

Further, since the memory circuit 121 and the logic circuit 122 areconnected only where they are good chips, defective wafers that are adefect of the WoW decrease, and therefore, occurrence of the yield losscan be reduced.

Furthermore, since the memory circuit 121 and the logic circuit to beconnected can be formed, different from the WoW, in a size as small aspossible irrespective of the chip size of the solid-state imagingelement 120 and arranged each in the shape of an independent island asindicated by the lower stage of FIG. 5, the theoretical yield of thememory circuit 12 and the logic circuit 122 to be connected can beimproved.

In this regard, since the solid-state imaging element 120 necessitates arequisite minimum pixel size for reacting with optical light, themanufacturing process for the solid-state imaging element 120 does notnecessarily require a fine wiring process, and therefore, the processcost can be reduced. Further, if the manufacturing process for the logiccircuit 122 uses a state-of-the-art fine wiring process, then the powerconsumption can be reduced. Furthermore, it is possible to improve thetheoretical yield of the memory circuit 121 and the logic circuit 122.As a result, the cost required for the manufacture of the solid-stateimaging device 111 can be reduced.

Further, since the solid-state imaging element 120 is structured suchthat chips can be rearranged on and joined to a wafer, heterogeneousprocesses by which analog circuits such as a power supply IC and a clockcircuit and the logic circuits 122 can be stacked in one chip even byheterogeneous processes by which it is difficult to manufacture circuitsconfigured by processes quite different from each other in the samewafer or even if there is a difference in wafer size.

Further, although the foregoing description is directed to an example inwhich the memory circuit 121 and the logic circuit 122 are used ascircuits to be connected to the solid-state imaging element 120, anysignal processing circuit other than the memory circuit 121 and thelogic circuit 122 may be connected if it is a signal processing circuitnecessitated for operation of the solid-state imaging element 120 suchas a circuit that relates to control of the solid-state imaging element120 or a circuit relating to processing of a captured pixel signal. Thesignal processing circuit necessitated for operation of the solid-stateimaging element 120 may be, for example, a power supply circuit, animage signal compression circuit, a clock circuit, an opticalcommunication conversion circuit or the like.

3. Second Embodiment

Although the foregoing description is given of the solid-state imagingdevice 111 having a two-layer structure in which a layer in which thesolid-state imaging element 120 is formed and a layer in which thememory circuit 121 and the logic circuit 122 are rearranged are stacked,the solid-state imaging device 111 may otherwise have a three-layerconfiguration.

FIG. 10 is a view illustrating a stack structure of wafers configured bythe WoW technology that is applied when a solid-state imaging device ofa three-layer structure of the present disclosure is manufactured.

In FIG. 10, a wafer 101 on which a solid-state imaging element 120 isformed, a wafer 201 on which a memory circuit 121 is rearranged and awafer 202 on which a logic circuit 122 is rearranged are stacked inorder from above.

The wafer 101 is similar to the wafer 101 of FIG. 4, and a plurality ofsolid-state imaging elements 120 is formed by a semiconductor process onthe wafer 101.

On the wafer 201, a plurality of memory circuits 121 that has beensubjected, after the memory circuits 121 have been formed on a wafer 103by a semiconductor process and singulated, to electric inspectionindividually and confirmed to be good chips is selected and rearranged.

On the wafer 202, a plurality of logic circuits 122 that has beensubjected, after the logic circuits 122 have been formed on a wafer 104by a semiconductor process and singulated, to electric inspectionindividually and confirmed to be good chips is selected and rearranged.

<Example of configuration of solid-state imaging device including wafersstacked by wow technology of FIG. 1>

The solid-state imaging device of the present disclosure is formed bysingulation of such wafers stacked by the WoW technology as depicted inFIG. 10. The solid-state imaging device of the present disclosure isconfigured, for example, in such a manner as depicted in FIG. 11. It isto be noted that, in FIG. 11, the upper stage is a side elevationalsectional view, and the lower stage is an arrangement view of thesolid-state imaging element 120, memory circuit 121 and logic circuit122 as viewed from above.

In particular, in the solid-state imaging device 111 at the upper stageof FIG. 11, an on-chip lens and on-chip color filter 131, a solid-stateimaging element 120, a memory circuit 121, a logic circuit 122 and asupport substrate 132 are formed in order from above in the figure. Inparticular, as depicted in the upper stage of FIG. 11, the solid-stateimaging device Ill of FIG. 11 has: a semiconductor element layer E11including a solid-state imaging element 120 including the wafer 101; asemiconductor element layer E12 including a memory circuit 121 formed onthe wafer 201; and a semiconductor element layer E13 including a logiccircuit 122 formed on the wafer 202.

Terminals 120 a of the solid-state imaging element 120 are electricallyconnected to the terminals 121 a-1 of the memory circuit 121 by wires134-1 connected by Cucu connection to the terminals 121 a-1.

Meanwhile, terminals 121 a-2 of the memory circuit 121 are electricallyconnected to the terminals 122 a of the logic circuit 122 by wires 134-2connected by CuCu connection to the terminals 122 a.

In a space around the solid-state imaging element 120, the memorycircuit 121, the logic circuit 122, and the support substrate 132, anoxide film 133 is formed. Further, on the boundary between thesemiconductor element layer E11 in which the solid-state imaging element120 is formed and the semiconductor element layer E12 in which thememory circuit 121 is formed such that it is embedded in the oxide film133, an oxide film joining layer 135 is formed and the layers are joinedtogether by oxide film joining. Furthermore, on the boundary between thesemiconductor element layer E12 in which the memory circuit 121 isformed in an embedded relation in the oxide film 133 and thesemiconductor element layer E13 in which the logic circuit 122 is formedin an embedded relation in the oxide film 133, an oxide film joininglayer 135 is formed, and the layers are joined together by oxide filmjoining. On the boundary between the semiconductor element layer E12 inwhich the logic circuit 122 is formed and the support substrate 132, anoxide film joining layer 135 is formed, and the layers are joinedtogether by oxide film joining.

Further, as depicted at the lower stage of FIG. 11, the memory circuit121 is formed at a substantially central position in the layer lowerthan the solid-state imaging element 120 and the logic circuit 122 isarranged at a substantially central position in the lower layer than thememory circuit 121 as viewed from above.

In particular, on the wafer 201 of FIG. 10, the memory circuit 121 isrearranged so as to coincide with a central position of the solid-stateimaging element 120 when each solid-state imaging devices 111 issingulated, and on the wafer 202, the logic circuit 122 is rearranged soas to coincide with a central position of the solid-state imagingelement 120.

<Manufacturing method of solid-state imaging device of FIG. 11>

Now, a manufacturing method of the solid-state imaging device 111 ofFIG. 11 is described with reference to FIGS. 12 and 13. It is to benoted that side elevational sectional views 12A to 12F in FIGS. 12 and13 depict side elevational sectional views of the solid-state imagingdevice 111.

At a first step, as depicted by the side elevational sectional view 12Aof FIG. 12, a solid-state imaging element 120 and a memory circuit 121are stacked on a support substrate 132-1 from above as depicted by theside elevational sectional view 12A of FIG. 12, and a space between thesolid-state imaging element 120 and the memory circuit 121 around thememory circuit 121 is in a state filled with an oxide film 133 such thatthe memory circuit 121 is filled in the oxide film 133.

It is to be noted that, since steps until the side elevational sectionalview 12A of FIG. 12 is formed are similar to those in the case whereonly the memory circuit 121 is formed by the steps of the sideelevational sectional view 6A of FIG. 6 to the side elevationalsectional view 6J of FIG. 9, and therefore, description of them isomitted.

At a second step, as depicted in the side elevational sectional view 12Bof FIG. 12, the support substrate 132-1 is removed, and wires 134-2 areformed at the terminals 121 a-2 of the memory circuit 121.

At a third step, as depicted by a range surrounded by an alternate longand short dashes line in the side elevational sectional view 12C of FIG.12, the logic circuit 122 on which the wires 134-2 are formed at theterminals 122 a and which is provided on a support substrate 132-2 ispositioned such that the memory circuits 121 and the wires 134-2 areopposed to each other.

It is to be noted that a portion surrounded by an alternate long andshort dashes line in which the memory circuit 121 is configured on thesupport substrate 132-2 is similar to that in the case where only thelogic circuit 122 is formed by the steps of the side elevationalsectional view 6A of FIG. 6 to the side elevational sectional view 6H ofFIG. 8, and therefore, description of them is omitted.

At a fourth step, as depicted in the side elevational sectional view 12Dof FIG. 13, a lower face portion of the memory circuit 121 and an upperface portion of the logic circuit 122 are coupled to each other by oxidefilm coupling, and the terminals 121 a-2 of the memory circuit 121 andthe terminals 122 a of the logic circuit 122 are connected to each othervia the wires 134-2. Consequently, the memory circuit 121, the logiccircuit 122, and the solid-state imaging element 120 are electricallyconnected to each other.

At a fifth step, as depicted by the side elevational sectional view 12Eof FIG. 13, the silicon layer of the solid-state imaging element 120 isthinned.

At a sixth step, as depicted by the side elevational sectional view 12Fof FIG. 13, the on-chip lens and on-chip color filter 131 is provided onthe solid-state imaging element 120 and singulation is performed,thereby to complete the solid-state imaging device 111.

In this manner, the solid-state imaging device 111 of a totaling threelayer structure including the first layer in which the solid-stateimaging element 120 is formed, the second layer in which the memorycircuit 121 is formed and the third layer in which the logic circuit 122are formed is manufactured.

Also, in such a configuration as described above, since circuitconnection between the solid-state imaging element 120, the memorycircuit 121, and the logic circuit 122 can be established throughterminals formed in a wire density of fine wires by a lithographytechnique of semiconductors similarly as in the WoW, the number ofconnection terminals can be increased and reduction of the powerconsumption can be anticipated.

Further, since the memory circuit 121 and the logic circuit 122 areconnected only where they are good chips, the yield of wafers, which isa defect of the WoW, can be decreased and occurrence of the yield losscan be reduced.

Furthermore, as depicted in the side elevational sectional views 12A to12C of FIG. 12 described above, a configuration of three or more layerscan be implemented by forming wires (rear face wires) on a lower face inthe figures.

4. Third Embodiment

<Example of configuration of solid-state imaging device in case wheresolid-state imaging element is smaller than memory circuit or logiccircuit>

Although the foregoing description is given of an example of a case inwhich the solid-state imaging element 120 is greater than both thememory circuit 121 and the logic circuit 122, it may be configuredotherwise such that it is smaller than at least any one of the memorycircuit 121 or the logic circuit 122.

FIG. 14 depicts an example of a configuration of the solid-state imagingdevice 111 having a two-layer configuration in the case where thesolid-state imaging element 120 is smaller than the memory circuit 121but is greater than the logic circuit 122.

In particular, as depicted at the upper portion of FIG. 14, asolid-state imaging element 120 is formed on a configuration that alayer in which a memory circuit 121 and a logic circuit 122 are formedis provided on a support substrate 132 and wires 134 are formed atterminals 121 a and 122 a. Further, the solid-state imaging element 120is provided at a position at which it extends between the memory circuit121 and the logic circuit 122 as viewed from above as indicated at thelower portion of FIG. 14. In particular, as depicted at the upper stageof FIG. 14, the solid-state imaging device 111 of FIG. 14 has: asemiconductor element layer E1 including the solid-state imaging element120 including the wafer 101; and a semiconductor element layer E2including the memory circuit 121 and the logic circuit 122 formed on thewafer 102.

It is to be noted that an insulating film including an oxide film 133 isformed around the solid-state imaging element 120.

<Manufacturing method of solid-state imaging device of FIG. 14>

Now, a manufacturing method of the solid-state imaging device 111 ofFIG. 14 is described with reference to FIGS. 15 and 16. It is to benoted that side elevational sectional views 15A to 15F of FIGS. 15 and16 depict side elevational sectional views of the solid-state imagingdevice 111.

At a first step, as depicted by the side elevational sectional view 15Aof FIG. 15, a memory circuit 121 and a logic circuit 122 are formed on asupport substrate 132 and are embedded into an insulating film includingan oxide film 133, and an oxide film joining layer 135 is formed on theuppermost layer. Further, wires 134 are formed at terminals 121 a and122 a.

It is to be noted that the steps up to the formation of the sideelevational sectional view 15A of FIG. 15 are similar to those in thecase where a memory circuit 121 and a logic circuit 122 are formed on asupport substrate 132 by the steps of the side elevational sectionalview 6A of FIG. 6 to the side elevational sectional view 6H of FIG. 9,and therefore, description of them is omitted.

At a second step, as depicted by the side elevational sectional view 15Bof FIG. 15, a singulated solid-state imaging element 120 is rearrangedon a rearrangement substrate 211, to which adhesive 212 is applied, suchthat the imaging face side thereof is opposed to the rearrangementsubstrate 211. Further, as depicted by the lower stage of FIG. 14, thesolid-state imaging element 120 is rearranged on the rearrangementsubstrate 211 at a position at which it extends between the memorycircuit 121 and the logic circuit 122 in a plane direction.

At a third step, as depicted by the side elevational sectional view 15Cof FIG. 15, the solid-state imaging element 120 having the state of theside elevational sectional view 15B is reversed, and wires 134 of thememory circuit 121 and the logic circuit 122 of the side elevationalsectional view 15A are connected by CuCu joining and besides opposinglayers are joined together by oxide film joining.

At a fourth step, as depicted by the side elevational sectional view 15Dof FIG. 16, the rearrangement substrate 211 is removed.

At a fifth step, as depicted by the side elevational sectional view 15Eof FIG. 16, the silicon layer of the solid-state imaging element 120 isthinned.

At a sixth step, as depicted by the side elevational sectional view 15Fof FIG. 16, an on-chip lens and on-chip color filter 131 is provided onthe solid-state imaging element 120, and the solid-state imaging device111 is completed therewith. It is to be noted that, in the presentexample, in the solid-state imaging element 120, memory circuit 121 andlogic circuit 122 are all singulated at a stage before they areassembled.

In this manner, also in the case where the size of the solid-stateimaging element 120 is smaller than that of the memory circuit 121 butgreater than that of the logic circuit 122, the solid-state imagingdevice 111 of the totaling two-layer structure including the first layerin which the solid-state imaging element 120 is formed and the secondlayer in which the memory circuit 121 and the logic circuit 122 areformed is manufactured.

Also, in such a configuration as described above, since circuitconnection between the solid-state imaging element 120, the memorycircuit 121, and the logic circuit 122 can be established throughterminals formed in a wire density of fine wires by a lithographytechnique of semiconductors similarly as in the WoW, the number ofconnection terminals can be increased and reduction of the powerconsumption can be anticipated.

Further, since the memory circuit 121 and the logic circuit 122 areconnected only where they are good chips, the yield of wafers, which isa defect of the WoW, can be decreased and occurrence of the yield losscan be reduced.

It is to be noted that, also in the case where the solid-state imagingelement 120 is smaller than the logic circuit 122 but is greater thanthe memory circuit 121, the solid-state imaging device 111 can bemanufactured by similar steps. Similarly, also in the case where thesolid-state imaging element 120 is smaller than both the logic circuit122 and the memory circuit 121, the solid-state imaging device 111 canbe manufactured by similar steps.

5. Fourth Embodiment

<Example of Configuration of Solid-State Imaging Device of Three-LayerStructure in Case where Solid-State Imaging Element is Smaller thanMemory Circuit and Logic Circuit>

Although the foregoing description is directed to an example of aconfiguration of the solid-state imaging device 111 of a two-layerstructure in the case where the solid-state imaging element 120 issmaller than the memory circuit 121 but is greater than the logiccircuit 122, the solid-state imaging device 111 may have a three-layerstructure even in the case where the solid-state imaging element 120 issmaller than the memory circuit 121 but is greater than the logiccircuit 122.

FIG. 17 depicts an example of a configuration of a solid-state imagingdevice 111 having a three-layer structure in the case where thesolid-state imaging element 120 is smaller than the memory circuit 121but is greater than the logic circuit 122.

In particular, as depicted by the upper portion of FIG. 17, a logiccircuit 122 is formed on a support substrate 132 such that it isoxide-film-coupled by an oxide film joining layer 135, and a memorycircuit 121 is formed on the logic circuit 122 such that it isoxide-film-coupled by the oxide film joining layer 135. Further, asolid-state imaging element 120 is formed on the memory circuit 121 suchthat it is oxide-film-coupled by the oxide film joining layer 135, andan on-chip lens and on-chip color filter 131 is formed on thesolid-state imaging element 120. In particular, as indicated by theupper stage of FIG. 17, the solid-state imaging device 111 of FIG. 17has: a semiconductor element layer E11 including the solid-state imagingelement 120 including the wafer 101; a semiconductor element layer E12including the memory circuit 121 formed on the wafer 201; and asemiconductor element layer E13 including the logic circuit 122 formedon the wafer 202.

Further, terminals 120 a of the solid-state imaging element 120 andterminals 121 a-1 of the memory circuit 121 are electrically connectedto each other by wires 134-1 through CuCu joining, and terminals 121 a-2of the memory circuit 121 and terminals 122 a of the logic circuit 122are electrically connected by wires 134-2 through CuCu joining.

In this case, as indicated by the lower portion of FIG. 17, thesolid-state imaging element 120, memory circuit 121 and logic circuit122 are formed such that the center positions thereof are aligned withone another.

It is to be noted that an insulating film including an oxide film 133 isformed around the solid-state imaging element 120.

As a manufacturing method of the solid-state imaging device 111 in FIG.17, it is sufficient if only the logic circuit 122 is formed by thesteps of the side elevational sectional view 6A of FIG. 6 to the sideelevational sectional view 6H of FIG. 8 and then the memory circuit 121is placed on the rearrangement substrate 211 as indicated by the sideelevational sectional view 15B of FIG. 15 and is connected to the logiccircuit 122 as indicated by the side elevational sectional view 15C ofFIG. 15, whereafter the solid-state imaging element 120 is formed by asimilar method. Therefore, description with reference to the drawings isomitted.

Also, in such a configuration as described above, since circuitconnection between the solid-state imaging element 120, the memorycircuit 121, and the logic circuit 122 can be established throughterminals formed in a wire density of fine wires by a lithographytechnique of semiconductors similarly as in the WoW, the number ofconnection terminals can be increased and reduction of the powerconsumption can be anticipated.

Further, since the memory circuit 121 and the logic circuit 122 areconnected only where they are good chips, the yield of wafers, which isa defect of the WoW, can be decreased and occurrence of the yield losscan be reduced.

It is to be noted that, also in the case where the solid-state imagingelement 120 is smaller than the logic circuit 122 but is greater thanthe memory circuit 121, the solid-state imaging device 111 can bemanufactured by similar steps. Similarly, also in the case where thesolid-state imaging element 120 is smaller than both the logic circuit122 and the memory circuit 121, the solid-state imaging device 111 canbe manufactured by similar steps.

6. Fifth Embodiment

<Example of configuration of solid-state imaging device in case wherememory circuit and logic circuit are formed directly on wafer ofsolid-state imaging element>

The foregoing description is directed to an example in which, after thememory circuit 121 and the logic circuit 122 are singulated and it isconfirmed that they are good chips, they are formed on the wafer 102(support substrate 132). However, a memory circuit 121 and a logiccircuit 122 that have been singulated and have been confirmed as goodchips may be formed directly on the solid-state imaging element 120 onthe wafer 101.

FIG. 18 is a view illustrating a manufacturing method of a solid-stateimaging device in which a memory circuit 121 and a logic circuit 122that have been singulated and have been confirmed as good chips areformed directly on a solid-state imaging element 120 on a wafer 101.

In particular, referring to FIG. 18, a plurality of solid-state imagingelements 120 is formed on a wafer 101 by a semiconductor process.Further, a plurality of memory circuits 121 that has been subjected,after the memory circuits 121 are formed on a wafer 103 by asemiconductor process and singulated, to electric inspection andconfirmed as good chips through the electric inspection and a pluralityof logic circuits 122 that has been subjected, after the logic circuits122 are formed on a wafer 104 by a semiconductor process and singulated,to electric inspection and confirmed as good chips through the electricinspection are selected and rearranged on the solid-state imagingelement 120 formed on the wafer 101. In other words, since the memorycircuits 121 and the logic circuits 122 having been confirmed as goodchips are rearranged on the solid-state imaging element 120, the memorycircuits 121 and the logic circuits 122 here are configured smaller thanthe solid-state imaging elements 120.

It is to be noted that an example of a configuration of a solid-stateimaging device 111 having a two-layer configuration in the case where amemory circuit 121 and a logic circuit 122 having been singulated andconfirmed as good chips are formed directly on the solid-state imagingelement 120 on the wafer 101 is similar to that of FIG. 5. Therefore,description of the example is omitted.

<Manufacturing method of solid-state imaging device of FIG. 14>

Now, a manufacturing method of the solid-state imaging device 111 ofFIG. 18 is described with reference to FIGS. 19 and 20. Side elevationalsectional views 19A to 19E of FIGS. 19 and 20 depict side elevationalsectional views of the solid-state imaging device 111.

At a first step, as depicted by the side elevational sectional view 19Aof FIG. 19, a memory circuit 121 and a logic circuit 122 that have beenconfirmed as good chips through electric inspection are formed on asolid-state imaging element 120 on a wafer 101 such that they have sucha layout as depicted in the lower stage of FIG. 5 and wires 134 areformed on terminals 120 a and 121 a. Further, positioning is performedsuch that wires 134 from the terminals 121 a of the memory circuit 121and terminals 122 a of the logic circuit 122 and wires 134 fromterminals 120 a of the solid-state imaging element 120 of the wafer 101are positioned in an appropriately opposing relation to each other andare connected by CuCu joining and besides opposing layers are joinedtogether by oxide film joining to form an oxide film joining layer 135.

At a second step, as depicted by the side elevational sectional view 19Bof FIG. 19, the silicon layer on the memory circuit 121 and an upperface portion in the figure of the logic circuit 122 is thinned to aheight that does not have an influence on properties of the device andan oxide film 133 that functions as an insulating film is formed suchthat the chip including the rearranged memory circuit 121 and logiccircuit 122 is embedded therein.

At a third step, as depicted by the side elevational sectional view 19Cof FIG. 19, a support substrate 132 is joined to an upper portion of thememory circuit 121 and the logic circuit 122. At this time, layers atwhich the support substrate 132 and the memory circuit 121 and logiccircuit 122 are opposed to each other are joined together by oxide filmjoining to form an oxide film joining layer 135.

At a fourth step, as depicted by the side elevational sectional view 19Dof FIG. 20, upside down is performed such that the solid-state imagingelement 120 comes to the top and the silicon layer that is an upperlayer in the figure of the solid-state imaging element 120 is thinned.

At a fifth step, as depicted by the side elevational sectional view 19Eof FIG. 20, an on-chip lens and on-chip color filter 131 is provided onthe solid-state imaging element 120 and singulation is performed tocomplete a solid-state imaging device 111.

It is to be noted that, at the first step, when the memory circuit 121and the logic circuit 122 are to be rearranged and joined to thesolid-state imaging element 120, after they are individually subjectedto hydrophilic treatment, they are contacted with each other in such astate that part of the singulated memory circuit 121 or logic circuit122 such as an end side or an end point is positioned with certainlywith respect to the solid-state imaging element 120, for example, asdepicted in the upper stage of FIG. 21. Then, as depicted in the lowerstage of FIG. 21, the memory circuit 121 or the logic circuit 122 isgradually contacted with the solid-state imaging element 120 beginning,from among portions of the same, with a portion near to the portioncontacted with the solid-state imaging element 120 until it is entirelycontacted and joined by oxide film joining.

After a portion such as an end side or an end point of the memorycircuit 121 or the logic circuit 122 is positioned with high accuratelyand contacted with the solid-state imaging element 120, the memorycircuit 121 or the logic circuit 122 is gradually contacted beginningwith a portion near to the contacted portion until it is rearranged inthis manner. Consequently, the alignment accuracy of the memory circuit121 and the logic circuit 122 with the solid-state imaging element 120can be improved.

Further, since the memory circuit 121 and the logic circuit aregradually joined entirely after part of the memory circuit 121 or thelogic circuit 122 and the solid-state imaging element 120 are contactedwith each other in the state in which they are positioned in thismanner, it is possible to join them while voids (air bubbles) appearingin the joining face are gradually pushed out.

As a result, since appearance of voids in a joining face can besuppressed, even if the solid-state imaging device 111 is placed into ahigh temperature state at a different manufacturing step or uponoperation, air in voids (air bubbles) is suppressed from expanding andexploding and the product accuracy can be improved. It is to be notedthat, also at the first step in the first embodiment describedhereinabove with reference to the side elevational sectional view 6A ofFIG. 6, the entirety of the memory circuit 121 and the logic circuit maybe joined gradually after part of the memory circuit 121 or the logiccircuit 122 and the solid-state imaging element 120 are contacted in apositioned state.

Further, at the second step, after the memory circuit 121 and logiccircuit 122 and the solid-state imaging element 120 are joined togetheras depicted at the upper stage of FIG. 22 (similarly to the lower stageof FIG. 21), the silicon layer at an upper face portion in the figuresof the memory circuit 121 and the logic circuit 122 is thinned to aheight with which the properties of the device are not influenced asdepicted at the lower stage of FIG. 22. Then, the memory circuit 121 andthe logic circuit 122 are embedded into an insulating film including theoxide film 133 and an oxide film joining layer 135 is formed on theflattened uppermost face, by which such a configuration as indicated bythe side elevational sectional view 19B of FIG. 19 is obtained.

By such manufacturing steps as described above, the solid-state imagingdevice 111 including the first layer in which the solid-state imagingelement 120 is formed and the second layer in which the memory circuit121 and the logic circuit 122 are formed is manufactured.

As a result, since the memory circuit 121 and the logic circuit 122 areconnected to the solid-state imaging element 120, the step of arrangingthem on a support substrate is eliminated and the man-hours can bereduced. Further, since the support substrate partly becomes unnecessaryin manufacture, the manufacturing cost can be reduced. Furthermore,since the memory circuit 121 and the logic circuit 122 are rearranged onthe solid-state imaging element 120 in a state in which they aredirectly positioned relative to each other, the alignment accuracy ofthe memory circuit 121 and the logic circuit 122 with respect to thesolid-state imaging element 120 can be improved.

7. Modification of Fifth Embodiment

<Modification of solid-state imaging device in case where memory circuitand logic circuit are formed directly on wafer of solid-state imagingelement>

Although the solid-state imaging apparatus described above is configuredsuch that the memory circuit 121 and the logic circuit 122 are embeddedin an insulating film including the oxide film 133 and the oxide filmjoining layer 135 is formed on a flattened uppermost face so as to havesuch a configuration as depicted in the side elevational sectional view19B of FIG. 19, high heat resistant resin may be applied or laminated inplace of the oxide film 133.

In particular, after a memory circuit 121 and a logic circuit 122 areformed on a solid-state imaging element 120 on a wafer 101, a high heatresistant resin 251 including an organic film or the like may be appliedto or laminated on the memory circuit 121 and the logic circuit 122 asdepicted at the upper stage of FIG. 23.

By joining the support substrate 132 in a state in which the high heatresistant resin 251 remains in the applied or laminated state asdepicted at the lower stage of FIG. 23, it becomes possible to paste thesupport substrate 132 without thinning a silicon layer at an upper faceportion of the memory circuit 121 and the logic circuit 122, and theman-hours can be reduced.

It is to be noted that the oxide film 133 that serves as an embeddingmember as an insulating film for the memory circuit 121 and the logiccircuit 122 preferably is a Si-based oxide film such as, for example,SiO2, SiO and SRO. Further, for the high heat resistant resin 241, apolyimide-based film of PI, PBO or the like or a polyamide-based film ispreferably used as a high heat resistant material including an organicfilm.

8. Sixth Embodiment

<Example of configuration of solid-state imaging device in case wherememory circuit and logic circuit are formed in plural layers on wafer onwhich solid-state imaging element is formed>

The foregoing description is directed to an example in which a memorycircuit 121 and a logic circuit 122 singulated and confirmed as goodchips are rearranged in one layer on a solid-state imaging element 120formed on a wafer 101 to form a solid-state imaging device. However, amemory circuit 121 and a logic circuit 122 confirmed as good chips maybe rearranged in a plurality of layers to form a solid-state imagingdevice.

FIG. 24 is a view illustrating a stacked structure of a wafer configuredby the WoW technology applied to a solid-state imaging device that ismanufactured by forming memory circuits 121 and logic circuits 122,which have been singulated and confirmed as good chips, in two layers ona solid-state imaging element 120 formed on a wafer 101 of the presentdisclosure.

In FIG. 24, a wafer 102 on which memory circuits 121 and logic circuits122 are rearranged and a wafer 101 on which memory circuits 121 andlogic circuits 122 are rearranged on a solid-state imaging element 120are stacked from above in the figure. It is to be noted that, in FIG.24, the wafer 102 and the wafer 101 are configured such that individualfaces thereof on which the memory circuit 121 and the logic circuit 122are rearranged are opposed to each other. In particular, in FIG. 24,that the memory circuits 121 and the logic circuits 122 on the wafer 102are indicated by broken lines represents that the face thereof on whichthe memory circuits 121 and the logic circuits 122 are reconfigured areopposed to the wafer 101.

<Example of configuration of solid-state imaging device including wafersstacked by wow technology in FIG. 24>

Such wafers stacked by the WoW technology as depicted in FIG. 24 aresingulated to form the solid-state imaging device of the presentdisclosure. The solid-state imaging device of the present disclosure hassuch a configuration as, for example, depicted by the side elevationalsectional view of FIG. 25.

In particular, the solid-state imaging device 111 of FIG. 25 includes anon-chip lens and on-chip color filter 131, a solid-state imaging element120, a memory circuit 121-11 and a logic circuit 122-11 in a first layerfrom above, a memory circuit 121-11 and a logic circuit 122-12 in asecond layer from above, and a support substrate 132.

In particular, as depicted in FIG. 25, the solid-state imaging device111 of FIG. 24 has: a semiconductor element layer E31 including asolid-state imaging element 120 including a wafer 101; a semiconductorelement layer E32 including a memory circuit 121-11 and a logic circuit122-11 of the first layer formed directly by rearrangement on thesolid-state imaging element 120; and a semiconductor element layer E33including a memory circuit 121-12 and a logic circuit 122-12 of thesecond layer formed on the wafer 102.

Terminals 120 a of the solid-state imaging element 120 are electricallyconnected to terminals 121 a-11 of the memory circuit 121-11 andterminals 122 a-11 of the logic circuit 122-11 of the semiconductorelement layer E32 by wires 134-11 connected by CuCu connection. Further,the terminals 121 a-11 of the memory circuit 121-11 and the terminals122 a-11 of the logic circuit 122-11 of the semiconductor element layerE32 are electrically connected to terminals 121 a-12 of the memorycircuit 121-12 and terminals 122 a-12 of the logic circuit 122-12 of thesemiconductor element layer E33 by wires 134-12 connected by CuCuconnection.

In a space around the solid-state imaging element 120, and the memorycircuits 121-11 and 121-12 and the logic circuits 122-11 and 122-12 ofthe semiconductor element layers E32 and E33, and the support substrate132, an oxide film 133 is formed. Further, on the boundary betweensemiconductor element layer E31 on which the solid-state imaging element120 is formed and the semiconductor element layer E32 in which thememory circuit 121-11 and the logic circuit 122-11 are formed andembedded in the oxide film 133, the oxide film joining layer 135 isformed and the layers are joined together by oxide film joining.Further, on the boundary between the semiconductor element layer E32 inwhich the memory circuit 121-11 and the logic circuit 122-11 are formedand embedded in the oxide film 133 and the semiconductor element layerE33 in which the memory circuit 121-12 and the logic circuit 122-12 areformed and embedded in the oxide film 133, the oxide film joining layer135 is formed and the layers are joined together by oxide film joining.On the boundary between the support substrate 132 and the semiconductorelement layer E33 in which the memory circuit 121-12 and the logiccircuit 122-12 are formed and embedded in the oxide film 133, the oxidefilm joining layer 135 is formed and the layers are joined together byoxide film joining.

<Manufacturing method of solid-state imaging device of FIG. 25>

Now, a manufacturing method of the solid-state imaging device 111 ofFIG. 25 is described with reference to FIGS. 26 to 28. It is to be notedthat side elevational sectional views 26A to 26G of FIGS. 26 to 28depict side elevational sectional views of the solid-state imagingdevice 111.

At a first step, as depicted by the side elevational sectional view 26Aof FIG. 26, after electric inspection for the solid-state imagingelement 120 on the wafer 101 is performed, memory circuits 121 and logiccircuits 122 that are confirmed as good products are formed in such alayout as depicted at the lower stage of FIG. 5 and wires 134-11 areformed to the terminals 120 a and 121 a. Further, positioning isperformed such that wires 134-11 from the terminals 121 a-11 of thememory circuit 121-11 and the terminals 122 a-11 of the logic circuit122-11 and the wires 134-11 from the terminals 120 a of the solid-stateimaging element 120 in the wafer 101 are positioned in an appropriatelyopposed relation to each other, and they are connected to each other byCuCu joining and the opposing layers are joined together by an oxidefilm joining layer 135 formed by oxide film joining.

At a second step, as depicted by the side elevational sectional view 26Bof FIG. 26, wires 134-12 formed, for example, from through-electrodes(TSVs) are formed for the terminals 121 a-11 of the memory circuit121-11 and the terminals 122 a-11 of the logic circuit 122-11.

At a third step, as depicted by the side elevational sectional view 26Cof FIG. 26, PADS for connection and an oxide film joining layer 135 forconnection are formed for the wires 134-12.

At a fourth step, as depicted by the side elevational sectional view 26Dof FIG. 27, terminals 121 a-12 of the memory circuit 121-12 andterminals 122 a-12 of the logic circuit 122-12 are formed in anelectrically connected state through the wires 134-12 by a methodsimilar to the method described hereinabove with reference to the sideelevational sectional views 19A and 19B of FIG. 19 and FIGS. 21 and 22.

At a fifth step, as depicted by the side elevational sectional view 26Eof FIG. 27, a support substrate 132 is joined to an upper portion of thememory circuit 121-12 and the logic circuit 122-12. At this time, theopposing layers of the support substrate 132 and the memory circuit121-12 and logic circuit 122-12 are joined together by an oxide filmjoining layer 135 formed by oxide film joining.

At a sixth step, as depicted by the side elevational sectional view 26Fof FIG. 27, upside down is performed such that the solid-state imagingelement 120 comes to the top and the silicon layer that is a layer atthe top in the figure of the solid-state imaging element 120 is thinned.

At a seventh step, as depicted by the side elevational sectional view26G of FIG. 28, an on-chip lens and on-chip color filter 131 is providedon the solid-state imaging element 120, and singulation is performed tocomplete the solid-state imaging device 111.

By such joining as described above, the memory circuit 121 and the logiccircuit 122 can be stacked in a plurality of layers.

It is to be noted that, although the foregoing description is directedto an example in which the memory circuit 121 and the logic circuit 122are formed in two layers, they may otherwise be stacked in three or morelayers by using a similar method.

9. Example of Connection to Solid-State Imaging Element First ConnectionExample

Although the foregoing description is directed to an example in which,in regard to joining, oxide film coupling is applied to portions otherthan terminals and CuCu joining is applied to terminals to form wires134 to establish electric connection, other connection methods may beused.

FIG. 29 depicts connection examples 29A to 29D in the case whereterminals 120 a and 122 a of a solid-state imaging element 120 and alogic circuit 122 within a range indicated by a frame Z11 of asolid-state imaging device Ill at a left upper stage are connected toeach other.

In the connection example 29A, the terminals 122 a of the logic circuit122 and the terminals 120 a of the solid-state imaging element 120 arearranged at a same position in a horizontal direction in the figure, andthe terminals 122 a of the logic circuits 122 are disposed in adisplaced relation to the boundary side with the solid-state imagingelement 120 in a vertical direction in the figure. Further, through-viasare formed such that they extend through the terminals 122 a and 120 afrom the rear face side (lower side in the figure) of the solid-stateimaging device 111, and a wire 134A is formed in each through-via.

In the connection example 29B, the terminals 122 a of the logic circuit122 and the terminals 120 a of the solid-state imaging element 120 arearranged in a displaced relation from each other in the horizontaldirection in the figure while the terminals 122 a of the logic circuit122 are arranged in a displaced relation to the boundary side with thesolid-state imaging element 120 in the vertical direction in the figure.Further, through-vias are formed such that they extend through theterminals 122 a and 120 a independently of each other from the rear faceside (lower side in the figure) of the solid-state imaging device 111.Further, wires 134B are formed in the through-vias, and wires areconnected to them on the surface on the rear face side.

In the connection example 29C, the terminals 122 a of the logic circuit122 and the terminals 120 a of the solid-state imaging element 120 arearranged at a same position in the horizontal direction in the figurewhile the terminals 122 a of the logic circuit 122 are arranged in adisplaced relation to the rear face side (lower side in the figure) fromthe solid-state imaging element 120 in the vertical direction in thefigure. Further, through-vias are formed such that they extend throughthe terminals 122 a and 120 a from the rear face side (lower side in thefigure) of the solid-state imaging device 111, and wires 134C are formedin the through-vias.

In the connection example 29D, the terminals 122 a of the logic circuit122 and the terminals 120 a of the solid-state imaging element 120 arearranged in a displaced relation from each other in the horizontaldirection in the figure while the terminals 122 a of the logic circuit122 are arranged in a displaced relation to the rear face side (lowerside in the figure) from the solid-state imaging element 120 in thevertical direction in the figure. Further, vias are formed such thatthey extend through the terminals 122 a and 120 a independently of eachother from the rear face side (lower side in the figure) of thesolid-state imaging device 111, and wires 134D are formed in the viasand wires are connected to them on the surface on the rear face side.

<Manufacturing method of solid-state imaging device in which connectionexamples to solid-state imaging element of FIG. 29 are used>

Now, a manufacturing method of the solid-state imaging device 111 forwhich the connection examples of FIG. 29 are used is described withreference FIGS. 30 to 32. It is to be noted that side elevationalsectional views 30A to 30H of FIGS. 30 to 32 depict side elevationalsectional views of the solid-state imaging device 111. Here, theconnection example 29A is described here.

At a first step, as depicted by the side elevational sectional view 30Aof FIG. 30, after electric inspection is performed, memory circuits 121and logic circuits 122 confirmed as good products are rearranged on therearrangement substrate 151 corresponding to the wafer 102. Therearrangement substrate 151 has adhesive 152 applied thereto, and thememory circuits 121 and the logic circuits 122 are rearranged on andfixed to the rearrangement substrate 151 by the adhesive 152. It is tobe noted that, after a portion such as an end face or an end point ofthe memory circuit 121 or the logic circuit 122 is contacted with thesolid-state imaging element 120, the other portion of the memory circuit121 or the logic circuit 122 is gradually contacted, joined andrearranged beginning with a portion near to the contacted portion asdescribed hereinabove with reference to FIG. 22.

At a second step, as depicted by the side elevational sectional view 30Bof FIG. 30, upside down is performed such that the upper face of thememory circuit 121 and the logic circuit 122 depicted in the sideelevational sectional view 30A comes to the bottom, and an oxide filmjoining layer 135 is formed on the solid-state imaging element 120 tocouple them to the solid-state imaging element 120 by oxide filmcoupling.

At a third step, as depicted by the side elevational sectional view 30Cof FIG. 30, the rearrangement substrate 151 is debonded, exfoliated andremoved together with the adhesive 152.

At a fourth step, as depicted by the side elevational sectional view 30Dof FIG. 31, the silicon layer at an upper face portion in the figure ofthe memory circuit 121 and the logic circuit 122 is thinned to a widththat does not have an influence on performances of the device.

At a fifth step, as depicted by the side elevational sectional view 30Eof FIG. 31, an oxide film 133 that functions as an insulating film isformed such that a chip including the rearranged memory circuit 121 andlogic circuit 122 is embedded in the oxide film 133 and then the oxidefilm 133 is flattened. Further, the terminals 121 a of the memorycircuit 121 and the terminals 120 a of the solid-state imaging element120 are arranged at a same position in the horizontal direction, andthrough-vias are formed so as to extend through the terminals 120 a and121 a. Thereafter, metal is embedded into the through-vias to form awire 134A in each of the through-vias.

At a sixth step, as depicted by the side elevational sectional view 30Fof FIG. 31, the configuration depicted in the side elevational sectionalview 30E is reversed, and an oxide film joining layer 135 is formed onthe support substrate 132 and then the configuration is coupled to thesupport substrate 132 by oxide film coupling.

At a seventh step, as depicted by the side elevational sectional view30G of FIG. 32, the silicon layer of the solid-state imaging element 120is thinned.

At an eighth step, as depicted by the side elevational sectional view30H of FIG. 32, an on-chip lens and on-chip color filter 131 is providedon the solid-state imaging element 120 and singulation is performed, anda solid-state imaging device 111 is completed therewith.

By such steps as described above, the wires 134A are formed in thethrough-vias formed to extend from the rear face side to establish astate in which the solid-state imaging element 120 and the memorycircuit 121 and logic circuit 122 are electrically connected to eachother, and the solid-state imaging device 111 is manufactured thereby.

It is to be noted that also the wires 134B to 134D depicted in theconnection examples 29B to 29C can be manufactured by similar stepsalthough they are different in terms of the position, depth and numberof through-vias.

Also, in such a configuration as described above, since circuitconnection between the solid-state imaging element 120 and the memorycircuit 121 and logic circuit 122 can be established through terminalsformed in a wire density of fine wires by a lithography technique ofsemiconductors similarly as in the WoW, the number of connectionterminals can be increased and reduction of the power consumption can beanticipated.

Second Connection Example

Although the foregoing description is directed to an example in which athrough-via is formed from the rear face side (from the opposite side tothe imaging face) of the solid-state imaging device 111 and a wire forelectrically connecting a terminal is formed, a wire may be formed byforming a through-via from the front face side (imaging face side) andpouring metal into the through-via.

FIG. 33 depicts connection examples 33A to 33D in the case where theterminals 120 a and 122 a of the solid-state imaging elements 120 andthe logic circuits 122 within a range indicated by a frame Z21 of thesolid-state imaging device 111 at the left upper stage are connected toeach other.

In the connection example 33A, the terminals 122 a of the logic circuits122 and the terminals 120 a of the solid-state imaging elements 120 arearranged at a same position in the horizontal direction in the figureand the terminals 122 a of the logic circuits 122 are arranged in adisplaced relation to the boundary side with the solid-state imagingelement 120 in the vertical direction in the figure. Further,through-vias are formed such that they extend in a skewered statethrough the terminals 122 a and 120 a from the front face side (upperside in the figure) of the solid-state imaging device 111 and wires 134Eare formed in the through-vias.

In the connection example 33B, the terminals 122 a of the logic circuits122 and the terminals 120 a of the solid-state imaging elements 120 arearranged in a displaced relation from each other in the horizontaldirection in the figure and the terminals 122 a of the logic circuits122 are arranged in a displaced relation to the boundary side with thesolid-state imaging element 120 in the vertical direction in the figure.Further, through-vias are formed such that they extend independently ofeach other through the terminals 122 a and 120 a from the front faceside (upper side in the figure) of the solid-state imaging device 111and wires 134F are formed in the through-vias, and the wires areconnected on the surface on the front face side.

In the connection example 33C, the terminals 122 a of the logic circuits122 and the terminals 120 a of the solid-state imaging elements 120 arearranged at a same position in the horizontal direction in the figureand the terminals 122 a of the logic circuits 122 are arranged in adisplaced relation to the rear face side (lower side in the figure) tothe solid-state imaging element 120 in the vertical direction in thefigure. Further, through-vias are formed such that they extend in askewered state through the terminals 122 a and 120 a from the front faceside (upper side in the figure) of the solid-state imaging device 111and wires 134G are formed in the through-vias.

In the connection example 33D, the terminals 122 a of the logic circuits122 and the terminals 120 a of the solid-state imaging elements 120 arearranged in a displacement relation from each other in the horizontaldirection in the figure and the terminals 122 a of the logic circuits122 are arranged in a displaced relation to the rear face side (lowerside in the figure) to the solid-state imaging element 120 in thevertical direction in the figure. Further, through-vias are formed suchthat they extend independently of each other through the terminals 122 aand 120 a from the front face side (upper side in the figure) of thesolid-state imaging device 111 and wires 134H are formed in thethrough-vias, and the wires are connected on the surface on the rearface side.

It is to be noted that, since it is necessary to form the through-viasfrom the imaging plane, all of the wires 134E to 134H are formed on theoutside of the pixel region of the solid-state imaging elements 120 inthe horizontal direction.

<Manufacturing method of solid-state imaging device in which connectionexamples to solid-state imaging element of FIG. 33 are used>

Now, a manufacturing method of the solid-state imaging device 111 forwhich the connection examples of FIG. 33 are used is described withreference to FIGS. 34 to 36. It is to be noted that side elevationalsectional views 34A to 34H of FIGS. 34 to 36 depict side elevationalsectional views of the solid-state imaging device 111. Further,description here is given of the connection example 33A.

At a first step, as depicted by the side elevational sectional view 34Aof FIG. 34, after electric inspection is performed, a memory circuit 121and a logic circuit 122 configured as good products are rearranged on arearrangement substrate 151 corresponding to a wafer 102. Therearrangement substrate 151 has adhesive 152 applied thereto, and thememory circuit 121 and the logic circuit 122 are rearranged on and fixedto the rearrangement substrate 151 by the adhesive 152. It is to benoted that, after a portion such as an end face or an end point of thememory circuit 121 or the logic circuit 122 is contacted with thesolid-state imaging element 120, the other portion of the memory circuit121 or the logic circuit 122 is gradually contacted, joined andrearranged beginning with a portion near to the contacted portion asdescribed hereinabove with reference to FIG. 22.

At a second step, as depicted by the side elevational sectional view 34Bof FIG. 34, upside down is performed such that the upper face of thememory circuit 121 and the logic circuit 122 depicted in the sideelevational sectional view 34B now becomes a lower face, and an oxidefilm joining layer 135 is formed on the solid-state imaging element 120to achieve oxide film joining.

At a third step, as depicted in the side elevational sectional view 34Cof FIG. 34, the rearrangement substrate 151 is debonded, exfoliated andremoved together with the adhesive 152.

At a fourth step, as depicted by the side elevational sectional view 34Dof FIG. 35, the silicon layer at an upper face portion in the figure ofthe memory circuit 121 and the logic circuit 122 is thinned to an extentthat does not have an influence on the performances of the device.

At a fifth step, as depicted by the side elevational sectional view 34Eof FIG. 35, an oxide film 133 that functions as an insulating film isformed such that the chip including the rearranged memory circuit 121and logic circuit 122 is embedded in the oxide film 133 and isflattened.

At a sixth step, as depicted by the side elevational sectional view 34Fof FIG. 35, the configuration depicted in the side elevational sectionalview 34F is reversed and an oxide film joining layer 135 is formed onthe support substrate 132 to achieve oxide film joining.

At a seventh step, as depicted by the side elevational sectional view34G of FIG. 36, the silicon layer of the solid-state imaging element 120is thinned. Further, the terminals 121 a of the memory circuit 121 andthe terminals 120 a of the solid-state imaging element 120 are arrangedat a same position in the horizontal direction, and through-vias areformed so as to extend through the terminals 120 a and 121 a from thefront face side such that the terminals 120 a and 121 a are placed intoa skewered state. Then, metal is embedded into the through-vias to formwires 134E.

At an eighth step, as depicted by the side elevational sectional view34H of FIG. 36, an on-chip lens and on-chip color filter 131 is providedon the solid-state imaging element 120, and singulation is performed tocomplete the solid-state imaging device 111.

By such steps as described above, the wires 134A are formed by thethrough-vias formed from the front face side (imaging face side) toestablish a state in which the solid-state imaging element 120 and thememory circuit 121 and logic circuit 122 are electrically connected toeach other, and the solid-state imaging device 111 is manufacturedthereby.

It is to be noted that also the wires 134F to 134H depicted in theconnection examples 33B to 33C can be manufactured by similar stepsalthough they are different in terms of the position, depth and numberof through-vias.

Also, in such a configuration as described above, since circuitconnection between the solid-state imaging element 120 and the memorycircuit 121 and logic circuit 122 can be established through terminalsformed in a wire density of fine wires by a lithography technique ofsemiconductors similarly as in the WoW, the number of connectionterminals can be increased and reduction of the power consumption can beanticipated.

10. Modification of Example of Connection to Solid-State Imaging Element

<First modification of connection example to solid-state imagingelement>

The electric connection between the solid-state imaging element 120 andthe memory circuit 121 and logic circuit 122 may be different from theconnection examples of FIGS. 29 and 33.

FIG. 37 depicts a modification of the electric connection examplebetween the solid-state imaging element 120 and the memory circuit 121and logic circuit 122 of the solid-state imaging device 111.

In FIG. 37, a first semiconductor substrate 321, a second semiconductorsubstrate 322 and a third semiconductor substrate 323 are stacked fromabove, and it is assumed that a solid-state imaging element 120 isformed in the first semiconductor substrate 321 while the memory circuit121 is formed in the second semiconductor substrate 322 and the logiccircuit 122 is formed in the third semiconductor substrate 323. It is tobe noted that the substrates in which the memory circuit 121 and thelogic circuit 122 are formed may be replaced with each other.

Further, in the first semiconductor substrate 321, the secondsemiconductor substrate 322, and the third semiconductor substrate 323,multilayer wiring layers 331, 332, and 333 for the solid-state imagingelement 120, the memory circuit 121, and the logic circuit 122 areformed, respectively. Further, in FIG. 37, the multilayer wiring layer332 is directed to the third semiconductor substrate 323, and themultilayer wiring layers 332 and 333 are structured such that they arepasted to each other on the boundary between the second semiconductorsubstrate 322 and the third semiconductor substrate 323.

Furthermore, pads 341 and 342 for external connection including metalsuch as, for example, aluminum are provided, and a signal to and from anexternal apparatus connected through a pad hole 350 is inputted andoutputted through a pad 341 connected to the pad 342.

As depicted in FIG. 37, the pad hole 350 is formed in the firstsemiconductor substrate 321 such that it extends to the pad 341 from therear face side (light receiving face side) of the first semiconductorsubstrate 321. Further, the pad 342 is formed in the multilayer wiringlayer 331 of the first semiconductor substrate 321.

Further, in the configuration of FIG. 37, a contact 351 used forelectric connection between the first semiconductor substrate 321 andthe second semiconductor substrate 322 and a contact 352 used forelectric connection between the second semiconductor substrate 322 andthe third semiconductor substrate 323 are provided. The contact 351 andthe contact 352 are configured as twin contacts.

In particular, for electric connection between the solid-state imagingelement 120 and the memory circuit 121 and logic circuit 122, the twincontacts 351 and 352 may be used as depicted in FIG. 37.

<Second modification of connection example to solid-state imagingelement>

As depicted in FIG. 38, the multilayer wiring layer 331 of the firstsemiconductor substrate 321 may be directed to the second semiconductorsubstrate 322 side (upper side in the figure) such that the multilayerwiring layers 331 and 332 are pasted to each other on the boundarybetween the first semiconductor substrate 321 and the secondsemiconductor substrate 322.

In the configuration of FIG. 38, different from that of the case of FIG.37, the pad 342 is provided in the multilayer wiring layer 332 of thesecond semiconductor substrate 322. Further, in the first semiconductorsubstrate 321, the pad hole 350 is formed so as to extend to the pad 341from the rear face side (light receiving face side) of the firstsemiconductor substrate 321.

Further, in the configuration of FIG. 38, a contact 361 used forelectric connection between the first semiconductor substrate 321 andthe second semiconductor substrate 322 and a contact 362 used forelectric connection between the second semiconductor substrate 322 andthe third semiconductor substrate 323 are provided. The contacts 361 and362 are configured as twin contacts.

In the case of the configuration of FIG. 38, different from that of thecase of FIG. 37, the contact 362 extends through the first semiconductorsubstrate 321 and the second semiconductor substrate 322 to themultilayer wiring layer 333 of the third semiconductor substrate 323.

In particular, as depicted in FIG. 38, for electric connection betweenthe solid-state imaging element 120 and the memory circuit 121 and logiccircuit 122, the twin contacts 361 and 362 may be used.

<Third modification of connection example to solid-state imagingelement>

In the configuration of FIG. 39, the first semiconductor substrate 321and the second semiconductor substrate 322 are pasted to each other suchthat an insulating film layer 371 for the second semiconductor substrate322 is directed to the third semiconductor substrate 323 side (lowerside in the figure).

Further, in the configuration of FIG. 39, similarly as in FIG. 37, acontact 351 used for electric connection between the first semiconductorsubstrate 321 and the second semiconductor substrate 322 and a contact352 used for electric connection between the second semiconductorsubstrate 322 and the third semiconductor substrate 323 are provided.The contacts 351 and 352 are configured as twin contacts.

Furthermore, in the configuration of FIG. 39, different from that of thecase of FIG. 37, the insulating film layer 371 is formed between thefirst semiconductor substrate 321 and the second semiconductor substrate322. Further, the pad 341 is arranged in the insulating film layer 371,and the pad 341 is connected to a contact 372 connected to themultilayer wiring layer 332 of the second semiconductor substrate 322.

Further, in the configuration of FIG. 39, the pad hole 350 is formed inthe first semiconductor substrate 321 such that it extends to the pad341 in the insulating film layer 371 from the rear face side (lightreceiving face side) of the first semiconductor substrate 321.

In particular, as depicted in FIG. 39, for electric connection betweenthe solid-state imaging element 120 and the memory circuit 121 and logiccircuit 122, the twin contacts 351 and 352 may be used. Further, the pad341 may be configured so as to be connected to the insulating film layer372 connected to the multilayer wiring layer 332 of the secondsemiconductor substrate 322.

<Fourth modification of connection example to solid-state imagingelement>

In the configuration of FIG. 40, similarly as in that of the case ofFIG. 37, the pad hole 350 is formed in the first semiconductor substrate321 such that it extends from the rear face side (light receiving faceside) of the first semiconductor substrate 321 to the pad 341. Further,the pad 342 is formed in the multilayer wiring layer 331 of the firstsemiconductor substrate 321.

In the configuration of FIG. 40, similarly to that in the case of FIG.37, the first semiconductor substrate 321 and the second semiconductorsubstrate 322 are pasted to each other such that the multilayer wiringlayer 332 of the second semiconductor substrate 322 is directed to thethird semiconductor substrate 323 side (lower side in the figure).

Further, in the configuration of FIG. 40, similarly as in the case ofFIG. 37, the contact 351 used for electric connection between the firstsemiconductor substrate 321 and the second semiconductor substrate 322is provided. The contact 351 is configured as a twin contact.

In the configuration of FIG. 40, different from that of the case of FIG.37, the contact 352 used for electric connection between the secondsemiconductor substrate 322 and the third semiconductor substrate 323 isnot provided. On the other hand, contacts 381 and 382 used for electricconnection between the second semiconductor substrate 322 and the thirdsemiconductor substrate 323 are provided.

Each of the contacts 381 and 382 is formed by providing a through holethat extends through the second semiconductor substrate 322 to themultilayer wiring layer 333 of the third semiconductor substrate 323 andembedding a conductor in the through hole. In particular, each of thecontacts 381 and 382 is configured so as to connect the multilayerwiring layer 332 of the second semiconductor substrate 322 and themultilayer wiring layer 333 of the third semiconductor substrate 323only by providing one through hole.

In short, each of the contacts 381 and 382 is configured as a sharedcontact.

Also, in the solid-state imaging devices 111 having the configurationsdescribed above with reference to FIGS. 37 to 39, a shared contact maybe used for electric connection between the first semiconductorsubstrate 321 and the second semiconductor substrate 322 or for electricconnection between the second semiconductor substrate 322 and the thirdsemiconductor substrate 323.

In particular, as depicted in FIG. 40, the twin contact 351 and thecontacts 381 and 382 may be used for electric connection between thesolid-state imaging element 120 and the memory circuit 121 and logiccircuit 122.

<Fifth modification of connection example to solid-state imagingelement>

In the configuration of FIG. 41, similarly as in the case of FIG. 37,the pad hole 350 is formed in the first semiconductor substrate 321 suchthat it extends to the pad 341 from the rear face side (light receivingface side) of the first semiconductor substrate 321. Further, the pad342 is formed in the multilayer wiring layer 331 of the firstsemiconductor substrate 321.

Further, in the configuration of FIG. 41, similarly to that in the caseof FIG. 37, the first semiconductor substrate 321 and the secondsemiconductor substrate 322 are pasted to each other such that themultilayer wiring layer 332 of the second semiconductor substrate 322 isdirected to the third semiconductor substrate 323 side (lower side inthe figure).

Furthermore, in the configuration of FIG. 41, a contact 391 used forelectric connection between the second semiconductor substrate 322 andthe third semiconductor substrate 323 is provided. The contact 391 isconfigured as a twin contact.

Further, in the configuration of FIG. 41, a metal wire 332 a in themultilayer wiring layer 332 of the second semiconductor substrate 322and a metal wire 333 a in the multilayer wiring layer 333 of the thirdsemiconductor substrate 323 are joined directly to each other.Furthermore, a metal wire 332 b in the multilayer wiring layer 332 and ametal wire 333 b in the multilayer wiring layer 333 are joined directlyto each other. Consequently, the second semiconductor substrate 322 andthe third semiconductor substrate 323 are electrically connected to eachother.

In short, in the case of the configuration of FIG. 41, not a contact butdirect joining is used for electric connection between the secondsemiconductor substrate 322 and the third semiconductor substrate 323.Accordingly, the manufacturing step can be simplified and the area onthe substrate can be reduced.

In particular, as depicted in FIG. 41, for electric connection betweenthe solid-state imaging element 120 and the memory circuit 121 and logiccircuit 122, the twin contact 391 and the metal wires 332 a, 333 a and332 b, 333 b may be used.

<Modification of connection example to solid-state imaging element ofsixth embodiment>

In the configuration of FIG. 42, different from that of the case of FIG.41, contacts 401 and 402 used for electric connection between the firstsemiconductor substrate 321 and the second semiconductor substrate 322are provided. In particular, in the case of the configuration of FIG.42, a lower side end portion of the left side in the figure of thecontact 401 is connected to an upper side end portion in the figure ofthe contact 402 to electrically connect the first semiconductorsubstrate 321 and the second semiconductor substrate 322 to each other.It is to be noted that the contact 401 is configured as a twin contact.

In the configuration of FIG. 42, it is not necessary to provide a holethat extends to the multilayer wiring layer 332 from the light receivingface, for example, as in the formation of the contact 391 of FIG. 41.Therefore, it is possible to perform formation of a contact more simply.

The configuration of the other part in FIG. 42 is similar to that of thecase of FIG. 41, and therefore, detailed description of the same isomitted.

In particular, as depicted in FIG. 42, for electric connection betweenthe solid-state imaging element 120 and the memory circuit 121 and logiccircuit 122, the twin contacts 401 and 402 and the metal wires 332 a,333 a and 332 b, 333 b may be used.

<<11. Heat Dissipation Structure>>

Since the solid-state imaging element 120 of high picture quality and ahigh frame rate is likely to generate heat, heat dissipation measuresare required. Since the solid-state imaging element 120 performs opticalsensing, the surface to be sensed takes in light, and therefore, a lens431 is arranged at a preceding stage to the solid-state imaging element120 and a space 432 of air exists as depicted by a side elevationalsectional view 43A of FIG. 43.

Heat generated in the solid-state imaging element 120 moves in responseto the thermal conductivity of the material. Since the thermalconductivity of the air is approximately 7000 times the thermalconductivity of silicon, almost all of the generated heat is dissipatednot through the space 432 of the air but through the material contactingwith the solid-state imaging element 120. Accordingly, for example, insuch a configuration as depicted in the side elevational sectional view43A of FIG. 43, heat generated by the solid-state imaging element 120moves to and is dissipated by the oxide film 133 and logic circuit 122and the support substrate 132 as indicated by arrow marks.

As depicted by the side elevational sectional view 43A of FIG. 43, thelogic circuit 122 (or memory circuit 121) is covered therearound withthe oxide film 133 in order to bury the height for flattening.

Since the thickness of the oxide film joining layer 135 of eachsubstrate is very small, the heat resistance is low. However, the heightof the logic circuit 122 (or the memory circuit 121) is great incomparison with the thickness of the oxide film joining layer 135, andthe thermal conductivity of the oxide film 133 is lower than that ofsilicon that is the material of the logic circuit 122 (or the memorycircuit 121). Therefore, the heat mobility differs between an area inwhich the logic circuit 122 (or the memory circuit 121) is connected andanother area that is covered with the oxide film 133.

It is to be noted that, in the side elevational sectional view 43A ofFIG. 43, a magnitude of an arrow mark represents a magnitude of the heatmobility, and it is represented that, as the arrow mark becomes great,the heat mobility becomes high and the heat dissipation efficiencybecomes high. In particular, in the side elevational sectional view 43Aof FIG. 43, it is represented that, since the thermal conductivity ofthe logic circuit 122 (or the memory circuit 121) is higher than that ofthe oxide film 133, the heat dissipation efficiency of the logic circuit122 (or the memory circuit 121) is higher.

Therefore, as depicted by the side elevational sectional view 43B ofFIG. 43, a dummy circuit 441 including silicon and similar to a memberconfiguring the logic circuit 122 (or the memory circuit 121) may beprovided in an area of the oxide film 133 in which the logic circuit 122(or the memory circuit 121) is not formed. Since the thermalconductivity of silicon configuring the dummy circuit 441 is higher thanthe thermal conductivity of the oxide film 133, heat dissipation can beperformed more efficiently than where heat is dissipated through theoxide film 133 as indicated by arrow marks.

As depicted by the side elevational sectional view 43B of FIG. 43, inthe case where the dummy circuit 441 is provided, when the WoWtechnology is applied for manufacturing, from among logic circuits 122formed on the wafer 104 by a semiconductor process, those logic circuits122 that are determined as good products as a result of electricinspection are rearranged on a wafer 451 as depicted in FIG. 44.

Thereupon, on the wafer 451, the dummy circuit 441 is rearranged inadvance around the logic circuit 122 (or the memory circuit 121) on thewafer 451 such that such arrangement as depicted by the side elevationalsectional view 43A of FIG. 43 is obtained. Then, after the wafer 101 onwhich the solid-state imaging element 120 is formed by a semiconductorprocess is positioned and stacked on the wafer 451, it is singulated tocomplete a solid-state imaging device 111.

<First Modification of Heat Dissipation Structure>

Although the foregoing description is directed to an example in whichthe dummy circuit 441 is arranged in place of the oxide film 133 aroundthe logic circuit 122 or the memory circuit 121, a dummy wire includingmetal having a higher thermal conductivity may be included for the dummycircuit 441.

For example, the dummy circuit 441 may further include a dummy wire 441a as depicted in FIG. 45.

In particular, in the case of FIG. 45, since the dummy wire 441 aincluding a metal having a thermal conductivity higher than that ofsilicon is included in the dummy circuit 441, heat can be dissipated ina higher efficiency.

<Second Modification of Heat Dissipation Structure>

Although the foregoing description is directed to an example in whichthe dummy circuit 441 including the dummy wire 441 a is provided inplace of the oxide film 133 around the logic circuit 122 or the memorycircuit 121 to improve the heat dissipation efficiency, a high thermalconductivity material member may be pasted to the rear side of thesupport substrate 132 to improve the heat dissipation efficiency.

FIG. 46 depicts an example of a configuration of the solid-state imagingdevice 111 in which a high thermal conductive material is pasted to therear side of the support substrate 132.

In particular, as depicted by the side elevational sectional view 46A, ahigh thermal conductivity material member 471 including a high thermalconductivity material is pasted to the rear side (lower side in thefigure) of the support substrate 132. The high thermal conductivitymaterial member 471 is, for example, SiC, AlN, SIN, Cu, Al, C or thelike.

In the case where the high thermal conductivity material member 471 ispasted to the rear side of the support substrate 132, when the WoWtechnology is used for manufacturing, as depicted by the perspectiveview 46B, a wafer 481 including the high thermal conductivity materialmember 471 is stacked under the wafer 201 on which, from among logiccircuits 122 formed on the wafer 104 by a semiconductor process, thoselogic circuits 122 that are deemed as good products as a result ofelectric inspection are rearranged.

In particular, in this case, three wafers including the wafer 101 onwhich the solid-state imaging elements 120 are formed by a semiconductorprocess, wafer 201 on which the logic circuits 122 of good products arerearranged and wafer 481 including the high thermal conductivitymaterial member 471 are stacked from above in the figure.

Further, as depicted by the side elevational sectional view 46C of FIG.46, the high thermal conductivity material member 471 may be formed in aspace around the logic circuit 122 and embedded into the oxide film 133.

<Third Modification of Heat Dissipation Structure>

Although the foregoing description is directed to an example in whichthe high thermal conductivity material member 471 is pasted to the rearside of the support substrate 132 to improve the heat dissipationefficiency, a heat radiation mechanism of the water cooled type may beprovided further by providing a waterway for circulating cooling waterin the high thermal conductivity material member 471.

FIG. 47 depicts an example of a configuration of the solid-state imagingdevice 111 in which a heat dissipation mechanism of the water cooledtype is formed to further improve the heat dissipation efficiency.

In particular, although the solid-state imaging device 111 of FIG. 47has, as depicted by the side elevational sectional view 47A of FIG. 47,a basic configuration similar to the configuration of the solid-stateimaging device 111 described hereinabove with reference to FIG. 46, awaterway 491 for cooling water is further provided in the high thermalconductivity material member 471.

By circulating cooling water in the waterway 491, a heat dissipationmechanism of the water cooled type is formed, and this makes it possibleto dissipate heat generated by the solid-state imaging element 120through the cooling water and dissipate heat more efficiently.

In the case where the heat dissipation mechanism of the water cooledtype is provided, as depicted by the perspective view 47B of FIG. 47,the wafers 101 and 201 to be stacked are stacked on the wafer 481 in astate in which the waterway 491 is formed such that it is positionedrelative to the solid-state imaging element 120 and the logic circuit122 of the wafers 101 and 201 to be stacked.

<Fourth Modification of Heat Dissipation Structure>

Although the foregoing description is directed to an example in which aregion that forms a gap is filled up with the oxide film 133 around thememory circuit 121 and the logic circuit 122 as depicted by the leftupper portion of FIG. 48, much time is required to fill up the oxidefilm 133, and therefore, the process cost increases.

Therefore, a gap in a peripheral portion of the memory circuit 121 andthe logic circuit 122 may be filled with an organic material member 495including an organic material in place of the oxide film 133 as depictedby the right upper portion of FIG. 48 to form a heat dissipationstructure.

However, if a peripheral portion of the memory circuit 121 and the logiccircuit 122 is filled up with the organic material member 495, then whenthe oxide film joining layer 135 is formed on the uppermost face, theflatness of the oxide film joining layer 135 is damaged by an influenceof heat or warping or swelling is generated by a difference in linearexpansion coefficient of the embedded material. Thus, pasting of thesupport substrate 132 is sometimes disabled.

Therefore, as indicated by the lower portion of FIG. 48, preferably thelayout is formed so as to minimize the gap based on the shape of theshape of the memory circuit 121, logic circuit 122 and dummy circuit441. By performing layout of them so as to minimize the gap in thismanner, the amount of use of the organic material member 495 is made tothe minimum necessity. Consequently, the influence of heat when theoxide film joining layer 135 is formed on the uppermost face and theinfluence of warping or swelling caused by a difference in linearexpansion coefficient of the embedded material can be minimized, andpasting to the support substrate 132 can be implemented.

12. Example of Application to Electronic Equipment

The imaging element described above can be applied to various electronicequipment such as, for example, an imaging apparatus such as a digitalstill camera or a digital video camera, a portable telephone set havingan imaging function or other equipment having an imaging function.

FIG. 49 is a block diagram depicting an example of a configuration of animaging apparatus as electronic equipment to which the presenttechnology is applied.

The imaging apparatus 501 depicted in FIG. 49 includes an optical system502, a shutter device 503, a solid-state imaging element 504, a drivecircuit 505, a signal processing circuit 506, a monitor 507 and a memory508 and can capture a still image and a moving image.

The optical system 502 includes one or a plurality of lenses andintroduces light (incident light) from an imaging target to thesolid-state imaging element 504 such that an image is formed on a lightreceiving face of the solid-state imaging element 504.

The shutter device 503 is arranged between the optical system 502 andthe solid-state imaging element 504 and controls a light irradiationperiod and a light blocking period to the solid-state imaging element504 under the control of the drive circuit 505.

The solid-state imaging element 504 includes a package including thesolid-state imaging element described hereinabove. The solid-stateimaging element 504 accumulates signal charge for a period of time inresponse to light of an image formed on the light receiving face thereofthrough the optical system 502 and the shutter device 503. The signalcharge accumulated in the solid-state imaging element 504 is transferredin accordance with a driving signal (timing signal) supplied from thedrive circuit 505.

The drive circuit 505 outputs driving signals for controlling transferoperation of the solid-state imaging element 504 and shutter operationof the shutter device 503 to drive the solid-state imaging element 504and the shutter device 503, respectively.

The signal processing circuit 506 performs various signal processes forsignal charge outputted from the solid-state imaging element 504. Animage (image data) obtained by the signal processes performed by thesignal processing circuit 506 is supplied to and displayed on themonitor 507 or is supplied to and stored (recorded) into the memory 508.

Also, in the imaging apparatus 501 configured in this manner, byapplying the solid-state imaging device 111 described hereinabove to theoptical system 502 and the solid-state imaging element 204, the yieldcan be improved and the cost required for manufacture can be reduced.

13. Example of Use of Imaging Element

FIG. 50 is a view depicting examples of use where the solid-stateimaging device 111 described hereinabove is used.

The imaging element described above can be used for various cases inwhich visible rays, infrared rays, ultraviolet rays, X-rays or the likeare used, for example, as described below.

An apparatus that captures an image to be used for appreciation such asa digital camera, a portable apparatus with a camera function and soforth

An apparatus used in traffic such as automotive sensors for capturingthe front, back, surrounding, inside and so forth of an automobile forsafe driving such as automatic stop, recognition of a state of thedriver and so forth, surveillance cameras for monitoring a travellingvehicle or a road, distance measurement sensors that perform distancemeasurement between vehicles and so forth and like sensors

An apparatus used in home appliances such as a TV, a refrigerator, anair conditioner and so forth in order to image a gesture of a user toperform apparatus operation according to the gesture

An apparatus for medical use or health care use such as an endoscope, anapparatus for angiography by light reception of infrared rays and soforth

An apparatus for security use such as surveillance cameras for securityapplications, cameras for person authentication and so forth

An apparatus for beauty such as skin measuring instruments for imagingthe skin, microscopes for imaging the scalp and so forth

An apparatus for sports use such as action cameras, wearable cameras andso forth for sports applications

An apparatus for agricultural use such as cameras for monitoring thestate of the fields, produces and so forth

14. Example of Application to Endoscopic Surgery System

The technology according to the present disclosure (present technology)can be applied to various products. For example, the technologyaccording to the present disclosure may be applied to an endoscopicsurgery system.

FIG. 51 is a view depicting an example of a schematic configuration ofan endoscopic surgery system to which the technology according to anembodiment of the present disclosure (present technology) can beapplied.

In FIG. 51, a state is illustrated in which a surgeon (medical doctor)11131 is using an endoscopic surgery system 11000 to perform surgery fora patient 11132 on a patient bed 11133. As depicted, the endoscopicsurgery system 11000 includes an endoscope 11100, other surgical tools11110 such as a pneumoperitoneum tube 11111 and an energy device 11112,a supporting arm apparatus 11120 which supports the endoscope 11100thereon, and a cart 11200 on which various apparatus for endoscopicsurgery are mounted.

The endoscope 11100 includes a lens barrel 11101 having a region of apredetermined length from a distal end thereof to be inserted into abody cavity of the patient 11132, and a camera head 11102 connected to aproximal end of the lens barrel 11101. In the example depicted, theendoscope 11100 is depicted which includes as a rigid endoscope havingthe lens barrel 11101 of the hard type. However, the endoscope 11100 mayotherwise be included as a flexible endoscope having the lens barrel11101 of the flexible type.

The lens barrel 11101 has, at a distal end thereof, an opening in whichan objective lens is fitted. A light source apparatus 11203 is connectedto the endoscope 11100 such that light generated by the light sourceapparatus 11203 is introduced to a distal end of the lens barrel 11101by a light guide extending in the inside of the lens barrel 11101 and isirradiated toward an observation target in a body cavity of the patient11132 through the objective lens. It is to be noted that the endoscope11100 may be a forward-viewing endoscope or may be an oblique-viewingendoscope or a side-viewing endoscope.

An optical system and an image pickup element are provided in the insideof the camera head 11102 such that reflected light (observation light)from the observation target is condensed on the image pickup element bythe optical system. The observation light is photo-electricallyconverted by the image pickup element to generate an electric signalcorresponding to the observation light, namely, an image signalcorresponding to an observation image. The image signal is transmittedas RAW data to a CCU 11201.

The CCU 11201 includes a central processing unit (CPU), a graphicsprocessing unit (GPU) or the like and integrally controls operation ofthe endoscope 11100 and a display apparatus 11202. Further, the CCU11201 receives an image signal from the camera head 11102 and performs,for the image signal, various image processes for displaying an imagebased on the image signal such as, for example, a development process(demosaic process).

The display apparatus 11202 displays thereon an image based on an imagesignal, for which the image processes have been performed by the CCU11201, under the control of the CCU 11201.

The light source apparatus 11203 includes a light source such as, forexample, a light emitting diode (LED) and supplies irradiation lightupon imaging of a surgical region to the endoscope 11100.

An inputting apparatus 11204 is an input interface for the endoscopicsurgery system 11000. A user can perform inputting of various kinds ofinformation or instruction inputting to the endoscopic surgery system11000 through the inputting apparatus 11204. For example, the user wouldinput an instruction or a like to change an image pickup condition (typeof irradiation light, magnification, focal distance or the like) by theendoscope 11100.

A treatment tool controlling apparatus 11205 controls driving of theenergy device 11112 for cautery or incision of a tissue, sealing of ablood vessel or the like. A pneumoperitoneum apparatus 11206 feeds gasinto a body cavity of the patient 11132 through the pneumoperitoneumtube 11111 to inflate the body cavity in order to secure the field ofview of the endoscope 11100 and secure the working space for thesurgeon. A recorder 11207 is an apparatus capable of recording variouskinds of information relating to surgery. A printer 11208 is anapparatus capable of printing various kinds of information relating tosurgery in various forms such as a text, an image or a graph.

It is to be noted that the light source apparatus 11203 which suppliesirradiation light when a surgical region is to be imaged to theendoscope 11100 may include a white light source which includes, forexample, an LED, a laser light source or a combination of them. Where awhite light source includes a combination of red, green, and blue (RGB)laser light sources, since the output intensity and the output timingcan be controlled with a high degree of accuracy for each color (eachwavelength), adjustment of the white balance of a picked up image can beperformed by the light source apparatus 11203. Further, in this case, iflaser beams from the respective RGB laser light sources are irradiatedtime-divisionally on an observation target and driving of the imagepickup elements of the camera head 11102 are controlled in synchronismwith the irradiation timings. Then images individually corresponding tothe R, G and B colors can be also picked up time-divisionally. Accordingto this method, a color image can be obtained even if color filters arenot provided for the image pickup element.

Further, the light source apparatus 11203 may be controlled such thatthe intensity of light to be outputted is changed for each predeterminedtime. By controlling driving of the image pickup element of the camerahead 11102 in synchronism with the timing of the change of the intensityof light to acquire images time-divisionally and synthesizing theimages, an image of a high dynamic range free from underexposed blockedup shadows and overexposed highlights can be created.

Further, the light source apparatus 11203 may be configured to supplylight of a predetermined wavelength band ready for special lightobservation. In special light observation, for example, by utilizing thewavelength dependency of absorption of light in a body tissue toirradiate light of a narrow band in comparison with irradiation lightupon ordinary observation (namely, white light), narrow band observation(narrow band imaging) of imaging a predetermined tissue such as a bloodvessel of a superficial portion of the mucous membrane or the like in ahigh contrast is performed. Alternatively, in special light observation,fluorescent observation for obtaining an image from fluorescent lightgenerated by irradiation of excitation light may be performed. Influorescent observation, it is possible to perform observation offluorescent light from a body tissue by irradiating excitation light onthe body tissue (autofluorescence observation) or to obtain afluorescent light image by locally injecting a reagent such asindocyanine green (ICG) into a body tissue and irradiating excitationlight corresponding to a fluorescent light wavelength of the reagentupon the body tissue. The light source apparatus 11203 can be configuredto supply such narrow-band light and/or excitation light suitable forspecial light observation as described above.

FIG. 52 is a block diagram depicting an example of a functionalconfiguration of the camera head 11102 and the CCU 11201 depicted inFIG. 51.

The camera head 11102 includes a lens unit 11401, an image pickup unit11402, a driving unit 11403, a communication unit 11404 and a camerahead controlling unit 11405. The CCU 11201 includes a communication unit11411, an image processing unit 11412 and a control unit 11413. Thecamera head 11102 and the CCU 11201 are connected for communication toeach other by a transmission cable 11400.

The lens unit 11401 is an optical system, provided at a connectinglocation to the lens barrel 11101. Observation light taken in from adistal end of the lens barrel 11101 is guided to the camera head 11102and introduced into the lens unit 11401. The lens unit 11401 includes acombination of a plurality of lenses including a zoom lens and afocusing lens.

The number of image pickup elements which is included by the imagepickup unit 11402 may be one (single-plate type) or a plural number(multi-plate type). Where the image pickup unit 11402 is configured asthat of the multi-plate type, for example, image signals correspondingto respective R, G and B are generated by the image pickup elements, andthe image signals may be synthesized to obtain a color image. The imagepickup unit 11402 may also be configured so as to have a pair of imagepickup elements for acquiring respective image signals for the right eyeand the left eye ready for three dimensional (3D) display. If 3D displayis performed, then the depth of a living body tissue in a surgicalregion can be comprehended more accurately by the surgeon 11131. It isto be noted that, where the image pickup unit 11402 is configured asthat of stereoscopic type, a plurality of systems of lens units 11401are provided corresponding to the individual image pickup elements.

Further, the image pickup unit 11402 may not necessarily be provided onthe camera head 11102. For example, the image pickup unit 11402 may beprovided immediately behind the objective lens in the inside of the lensbarrel 11101.

The driving unit 11403 includes an actuator and moves the zoom lens andthe focusing lens of the lens unit 11401 by a predetermined distancealong an optical axis under the control of the camera head controllingunit 11405. Consequently, the magnification and the focal point of apicked up image by the image pickup unit 11402 can be adjusted suitably.

The communication unit 11404 includes a communication apparatus fortransmitting and receiving various kinds of information to and from theCCU 11201. The communication unit 11404 transmits an image signalacquired from the image pickup unit 11402 as RAW data to the CCU 11201through the transmission cable 11400.

In addition, the communication unit 11404 receives a control signal forcontrolling driving of the camera head 11102 from the CCU 11201 andsupplies the control signal to the camera head controlling unit 11405.The control signal includes information relating to image pickupconditions such as, for example, information that a frame rate of apicked up image is designated, information that an exposure value uponimage picking up is designated and/or information that a magnificationand a focal point of a picked up image are designated.

It is to be noted that the image pickup conditions such as the framerate, exposure value, magnification or focal point may be designated bythe user or may be set automatically by the control unit 11413 of theCCU 11201 on the basis of an acquired image signal. In the latter case,an auto exposure (AE) function, an auto focus (AF) function and an autowhite balance (AWB) function are incorporated in the endoscope 11100.

The camera head controlling unit 11405 controls driving of the camerahead 11102 on the basis of a control signal from the CCU 11201 receivedthrough the communication unit 11404.

The communication unit 11411 includes a communication apparatus fortransmitting and receiving various kinds of information to and from thecamera head 11102. The communication unit 11411 receives an image signaltransmitted thereto from the camera head 11102 through the transmissioncable 11400.

Further, the communication unit 11411 transmits a control signal forcontrolling driving of the camera head 11102 to the camera head 11102.The image signal and the control signal can be transmitted by electricalcommunication, optical communication or the like.

The image processing unit 11412 performs various image processes for animage signal in the form of RAW data transmitted thereto from the camerahead 11102.

The control unit 11413 performs various kinds of control relating toimage picking up of a surgical region or the like by the endoscope 11100and display of a picked up image obtained by image picking up of thesurgical region or the like. For example, the control unit 11413 createsa control signal for controlling driving of the camera head 11102.

Further, the control unit 11413 controls, on the basis of an imagesignal for which image processes have been performed by the imageprocessing unit 11412, the display apparatus 11202 to display a pickedup image in which the surgical region or the like is imaged. Thereupon,the control unit 11413 may recognize various objects in the picked upimage using various image recognition technologies. For example, thecontrol unit 11413 can recognize a surgical tool such as forceps, aparticular living body region, bleeding, mist when the energy device11112 is used and so forth by detecting the shape, color and so forth ofedges of objects included in a picked up image. The control unit 11413may cause, when it controls the display apparatus 11202 to display apicked up image, various kinds of surgery supporting information to bedisplayed in an overlapping manner with an image of the surgical regionusing a result of the recognition. Where surgery supporting informationis displayed in an overlapping manner and presented to the surgeon11131, the burden on the surgeon 11131 can be reduced and the surgeon11131 can proceed with the surgery with certainty.

The transmission cable 11400 which connects the camera head 11102 andthe CCU 11201 to each other is an electric signal cable ready forcommunication of an electric signal, an optical fiber ready for opticalcommunication or a composite cable ready for both of electrical andoptical communications.

Here, while, in the example depicted, communication is performed bywired communication using the transmission cable 11400, thecommunication between the camera head 11102 and the CCU 11201 may beperformed by wireless communication.

An example of an endoscopic surgery system to which the technologyaccording to the present disclosure can be applied has been described.The technology according to the present disclosure can be applied to theendoscope 11100, (image pickup unit 11402 of the) camera head 11102, andso forth among the components described hereinabove. In particular, thesolid-state imaging device 111 of the present disclosure can be appliedto the image pickup unit 10402. By applying the technology of thepresent disclosure to the endoscope 11100, (image pickup unit 11402 ofthe) camera head 11102 or the like, it is possible to improve the yieldand reduce the cost required for manufacture.

It is to be noted here that, although the endoscopic surgery system hasbeen described as an example, the technology according to the presentdisclosure may be further applied, for example, to a microscopic surgerysystem or the like.

15. Example of Application to Mobile Body

The technology according to the present disclosure (present technology)can be applied to various products. For example, the technologyaccording to the present disclosure may be implemented as an apparatusincorporated in a mobile body of any type such as, for example, anautomobile, an electric vehicle, a hybrid electric vehicle, amotorcycle, a bicycle, a personal mobility, an airplane, a drone, aship, a robot and so forth.

FIG. 53 is a block diagram depicting an example of schematicconfiguration of a vehicle control system as an example of a mobile bodycontrol system to which the technology according to an embodiment of thepresent disclosure can be applied.

The vehicle control system 12000 includes a plurality of electroniccontrol units connected to each other via a communication network 12001.In the example depicted in FIG. 53, the vehicle control system 12000includes a driving system control unit 12010, a body system control unit12020, an outside-vehicle information detecting unit 12030, anin-vehicle information detecting unit 12040, and an integrated controlunit 12050. In addition, a microcomputer 12051, a sound/image outputsection 12052, and a vehicle-mounted network interface (I/F) 12053 areillustrated as a functional configuration of the integrated control unit12050.

The driving system control unit 12010 controls the operation of devicesrelated to the driving system of the vehicle in accordance with variouskinds of programs. For example, the driving system control unit 12010functions as a control device for a driving force generating device forgenerating the driving force of the vehicle, such as an internalcombustion engine, a driving motor, or the like, a driving forcetransmitting mechanism for transmitting the driving force to wheels, asteering mechanism for adjusting the steering angle of the vehicle, abraking device for generating the braking force of the vehicle, and thelike.

The body system control unit 12020 controls the operation of variouskinds of devices provided to a vehicle body in accordance with variouskinds of programs. For example, the body system control unit 12020functions as a control device for a keyless entry system, a smart keysystem, a power window device, or various kinds of lamps such as aheadlamp, a backup lamp, a brake lamp, a turn signal, a fog lamp, or thelike. In this case, radio waves transmitted from a mobile device as analternative to a key or signals of various kinds of switches can beinput to the body system control unit 12020. The body system controlunit 12020 receives these input radio waves or signals, and controls adoor lock device, the power window device, the lamps, or the like of thevehicle.

The outside-vehicle information detecting unit 12030 detects informationabout the outside of the vehicle including the vehicle control system12000. For example, the outside-vehicle information detecting unit 12030is connected with an imaging section 12031. The outside-vehicleinformation detecting unit 12030 makes the imaging section 12031 imagean image of the outside of the vehicle, and receives the imaged image.On the basis of the received image, the outside-vehicle informationdetecting unit 12030 may perform processing of detecting an object suchas a human, a vehicle, an obstacle, a sign, a character on a roadsurface, or the like, or processing of detecting a distance thereto.

The imaging section 12031 is an optical sensor that receives light, andwhich outputs an electric signal corresponding to a received lightamount of the light. The imaging section 12031 can output the electricsignal as an image, or can output the electric signal as informationabout a measured distance. In addition, the light received by theimaging section 12031 may be visible light, or may be invisible lightsuch as infrared rays or the like.

The in-vehicle information detecting unit 12040 detects informationabout the inside of the vehicle. The in-vehicle information detectingunit 12040 is, for example, connected with a driver state detectingsection 12041 that detects the state of a driver. The driver statedetecting section 12041, for example, includes a camera that images thedriver. On the basis of detection information input from the driverstate detecting section 12041, the in-vehicle information detecting unit12040 may calculate a degree of fatigue of the driver or a degree ofconcentration of the driver, or may determine whether the driver isdozing.

The microcomputer 12051 can calculate a control target value for thedriving force generating device, the steering mechanism, or the brakingdevice on the basis of the information about the inside or outside ofthe vehicle which information is obtained by the outside-vehicleinformation detecting unit 12030 or the in-vehicle information detectingunit 12040, and output a control command to the driving system controlunit 12010. For example, the microcomputer 12051 can perform cooperativecontrol intended to implement functions of an advanced driver assistancesystem (ADAS) which functions include collision avoidance or shockmitigation for the vehicle, following driving based on a followingdistance, vehicle speed maintaining driving, a warning of collision ofthe vehicle, a warning of deviation of the vehicle from a lane, or thelike.

In addition, the microcomputer 12051 can perform cooperative controlintended for automatic driving, which makes the vehicle to travelautonomously without depending on the operation of the driver, or thelike, by controlling the driving force generating device, the steeringmechanism, the braking device, or the like on the basis of theinformation about the outside or inside of the vehicle which informationis obtained by the outside-vehicle information detecting unit 12030 orthe in-vehicle information detecting unit 12040.

In addition, the microcomputer 12051 can output a control command to thebody system control unit 12020 on the basis of the information about theoutside of the vehicle which information is obtained by theoutside-vehicle information detecting unit 12030. For example, themicrocomputer 12051 can perform cooperative control intended to preventa glare by controlling the headlamp so as to change from a high beam toa low beam, for example, in accordance with the position of a precedingvehicle or an oncoming vehicle detected by the outside-vehicleinformation detecting unit 12030.

The sound/image output section 12052 transmits an output signal of atleast one of a sound and an image to an output device capable ofvisually or auditorily notifying information to an occupant of thevehicle or the outside of the vehicle. In the example of FIG. 53, anaudio speaker 12061, a display section 12062, and an instrument panel12063 are illustrated as the output device. The display section 12062may, for example, include at least one of an on-board display and ahead-up display.

FIG. 54 is a diagram depicting an example of the installation positionof the imaging section 12031.

In FIG. 54, the imaging section 12031 includes imaging sections 12101,12102, 12103, 12104, and 12105.

The imaging sections 12101, 12102, 12103, 12104, and 12105 are, forexample, disposed at positions on a front nose, sideview mirrors, a rearbumper, and a back door of the vehicle 12100 as well as a position on anupper portion of a windshield within the interior of the vehicle. Theimaging section 12101 provided to the front nose and the imaging section12105 provided to the upper portion of the windshield within theinterior of the vehicle obtain mainly an image of the front of thevehicle 12100. The imaging sections 12102 and 12103 provided to thesideview mirrors obtain mainly an image of the sides of the vehicle12100. The imaging section 12104 provided to the rear bumper or the backdoor obtains mainly an image of the rear of the vehicle 12100. Theimaging section 12105 provided to the upper portion of the windshieldwithin the interior of the vehicle is used mainly to detect a precedingvehicle, a pedestrian, an obstacle, a signal, a traffic sign, a lane, orthe like.

Incidentally, FIG. 54 depicts an example of photographing ranges of theimaging sections 12101 to 12104. An imaging range 12111 represents theimaging range of the imaging section 12101 provided to the front nose.Imaging ranges 12112 and 12113 respectively represent the imaging rangesof the imaging sections 12102 and 12103 provided to the sideviewmirrors. An imaging range 12114 represents the imaging range of theimaging section 12104 provided to the rear bumper or the back door. Abird's-eye image of the vehicle 12100 as viewed from above is obtainedby superimposing image data imaged by the imaging sections 12101 to12104, for example.

At least one of the imaging sections 12101 to 12104 may have a functionof obtaining distance information. For example, at least one of theimaging sections 12101 to 12104 may be a stereo camera constituted of aplurality of imaging elements, or may be an imaging element havingpixels for phase difference detection.

For example, the microcomputer 12051 can determine a distance to eachthree-dimensional object within the imaging ranges 12111 to 12114 and atemporal change in the distance (relative speed with respect to thevehicle 12100) on the basis of the distance information obtained fromthe imaging sections 12101 to 12104, and thereby extract, as a precedingvehicle, a nearest three-dimensional object in particular that ispresent on a traveling path of the vehicle 12100 and which travels insubstantially the same direction as the vehicle 12100 at a predeterminedspeed (for example, equal to or more than 0 km/hour). Further, themicrocomputer 12051 can set a following distance to be maintained infront of a preceding vehicle in advance, and perform automatic brakecontrol (including following stop control), automatic accelerationcontrol (including following start control), or the like. It is thuspossible to perform cooperative control intended for automatic drivingthat makes the vehicle travel autonomously without depending on theoperation of the driver or the like.

For example, the microcomputer 12051 can classify three-dimensionalobject data on three-dimensional objects into three-dimensional objectdata of a two-wheeled vehicle, a standard-sized vehicle, a large-sizedvehicle, a pedestrian, a utility pole, and other three-dimensionalobjects on the basis of the distance information obtained from theimaging sections 12101 to 12104, extract the classifiedthree-dimensional object data, and use the extracted three-dimensionalobject data for automatic avoidance of an obstacle. For example, themicrocomputer 12051 identifies obstacles around the vehicle 12100 asobstacles that the driver of the vehicle 12100 can recognize visuallyand obstacles that are difficult for the driver of the vehicle 12100 torecognize visually. Then, the microcomputer 12051 determines a collisionrisk indicating a risk of collision with each obstacle. In a situationin which the collision risk is equal to or higher than a set value andthere is thus a possibility of collision, the microcomputer 12051outputs a warning to the driver via the audio speaker 12061 or thedisplay section 12062, and performs forced deceleration or avoidancesteering via the driving system control unit 12010. The microcomputer12051 can thereby assist in driving to avoid collision.

At least one of the imaging sections 12101 to 12104 may be an infraredcamera that detects infrared rays. The microcomputer 12051 can, forexample, recognize a pedestrian by determining whether or not there is apedestrian in imaged images of the imaging sections 12101 to 12104. Suchrecognition of a pedestrian is, for example, performed by a procedure ofextracting characteristic points in the imaged images of the imagingsections 12101 to 12104 as infrared cameras and a procedure ofdetermining whether or not it is the pedestrian by performing patternmatching processing on a series of characteristic points representingthe contour of the object. When the microcomputer 12051 determines thatthere is a pedestrian in the imaged images of the imaging sections 12101to 12104, and thus recognizes the pedestrian, the sound/image outputsection 12052 controls the display section 12062 so that a squarecontour line for emphasis is displayed so as to be superimposed on therecognized pedestrian. The sound/image output section 12052 may alsocontrol the display section 12062 so that an icon or the likerepresenting the pedestrian is displayed at a desired position.

An example of a vehicle control system to which the technology accordingto the present disclosure can be applied has been described. Thetechnology according to the present disclosure can be applied, forexample, to the imaging section 12031 and so forth from among thecomponents described above. In particular, the solid-state imagingdevice 111 of the present disclosure can be applied to the imagingsection 12031. By applying the technology according to the presentdisclosure to the imaging section 12031, it is possible to improve theyield and reduce the cost required for manufacture.

The technology according to the present disclosure can be applied tosuch a solid-state imaging device as described above.

It is to be noted that the present disclosure can have suchconfigurations as described below.

<1> A backside illumination type solid-state imaging device including:

a first semiconductor element including an imaging element configured togenerate a pixel signal in a unit of a pixel;

a second semiconductor element in which signal processing circuitsnecessary for signal processing of the pixel signal are embedded by anembedding member; and

a wire that electrically connects the first semiconductor element andthe second semiconductor element;

-   -   the first semiconductor element and the second semiconductor        element being stacked by oxide film joining.

<2> The backside illumination type solid-state imaging device accordingto <1>, in which

the first semiconductor element is greater than the second semiconductorelement.

<3> The backside illumination type solid-state imaging device accordingto <1>, in which

the first semiconductor element is smaller than the second semiconductorelement.

<4> The backside illumination type solid-state imaging device accordingto any one of <1> to <3>, in which

the signal processing circuits include a first signal processing circuitand a second signal processing circuit, and

the second semiconductor element has therein the first signal processingcircuit and the second signal processing circuit arranged in ajuxtaposed relation in a horizontal direction and embedded by theembedding member.

<5> The backside illumination type solid-state imaging device accordingto any one of <1> to <4>, in which

the signal processing circuits include a first signal processing circuitand a second signal processing circuit,

the wire includes a first wire and a second wire,

the second semiconductor element has therein the first signal processingcircuit embedded by the embedding member,

the solid-state imaging device includes a third semiconductor element inwhich the second signal processing circuit is embedded by the embeddingmember,

the first wire electrically connects the first semiconductor element andthe second semiconductor element to each other,

the second wire electrically connects the second semiconductor elementand the third semiconductor element to each other, and

the second semiconductor element and the third semiconductor element arestacked by oxide film joining.

<6> The backside illumination type solid-state imaging device accordingto any one of <1> to <5>, in which

the wire is joined by CuCu joining.

<7> The backside illumination type solid-state imaging device accordingto any one of <1> to <5>, in which

the wire electrically connects the first semiconductor element and thesecond semiconductor element through a through-via.

<8> The backside illumination type solid-state imaging device accordingto <7>, in which

the wire electrically connects the first semiconductor element and thesecond semiconductor element through a through-via formed from animaging face side of the imaging element.

<9> The backside illumination type solid-state imaging device accordingto <7>, in which

the wire electrically connects the first semiconductor element and thesecond semiconductor element through a through-via formed from a face onan opposite side to an imaging face of the imaging element.

<10> The backside illumination type solid-state imaging device accordingto any one of <1> to <9>, in which

the embedding member includes an oxide film.

<11> The backside illumination type solid-state imaging device accordingto any one of <1> to <9>, in which

the embedding member includes an organic material.

<12> The backside illumination type solid-state imaging device accordingto <11>, in which,

in the second semiconductor element, the signal processing circuits arelaid out such that a gap between the signal processing circuits isminimized, and the gap is filled with the embedding member including theorganic material.

<13> The backside illumination type solid-state imaging device accordingto any one of <1> to <12>, in which,

in the second semiconductor element, in addition to the signalprocessing circuits, a dummy circuit configured from a semiconductorelement and including a dummy wire is embedded by the embedding member.

<14> The backside illumination type solid-state imaging device accordingto any one of <1> to <13>, in which

a heat dissipation member that includes a member having a thermalconductivity higher than a predetermined thermal conductivity anddissipates heat is stacked on a face of the second semiconductor elementopposite to a face on which the first semiconductor element is stacked.

<15> The backside illumination type solid-state imaging device accordingto <14>, in which

the heat dissipation member includes SiC, AlN, SIN, Cu, Al, and C.

<16> The backside illumination type solid-state imaging device accordingto <14>, in which

the heat dissipation member includes a waterway for circulating coolingwater.

<17> The backside illumination type solid-state imaging device accordingto any one of <1> to <16>, in which

the signal processing circuits include a logic circuit, a memorycircuit, a power supply circuit, an image signal compression circuit, aclock circuit, and an optical communication conversion circuit.

<18> The backside illumination type solid-state imaging device accordingto any one of <1> to <17>, in which

the signal processing circuits are embedded in the first semiconductorelement by the embedding member.

<19> The backside illumination type solid-state imaging device accordingto <18>, in which

the signal processing circuits are each embedded by the embedding memberafter contacted at part thereof in a positioned state with the firstsemiconductor element and gradually joined to the first semiconductorelement beginning with a portion around the contacted portion.

<20> The backside illumination type solid-state imaging device accordingto <19>, in which

the part includes an end side and an end point of the signal processingcircuit.

<21> The backside illumination type solid-state imaging device accordingto <19>, in which

the signal processing circuit is smaller than the first semiconductorelement.

<22> The backside illumination type solid-state imaging device accordingto any one of <1> to <17>, in which

the signal processing circuits are each embedded by the embedding memberafter contacted at part thereof in a positioned state with the secondsemiconductor element and gradually joined to the second semiconductorelement beginning with a portion around the contacted portion.

<23> The backside illumination type solid-state imaging device accordingto <22>, in which

the part includes an end side and an end point of the signal processingcircuit.

<24> A manufacturing method for a backside illumination type solid-stateimaging device that includes

a first semiconductor element including an imaging element configured togenerate a pixel signal in a unit of a pixel,

a second semiconductor element in which signal processing circuitsnecessary for signal processing of the pixel signal are embedded by anembedding member, and

a wire that electrically connects the first semiconductor element andthe second semiconductor element,

the first semiconductor element and the second semiconductor elementbeing stacked by oxide film joining, wherein

a first wafer including the imaging element formed by a semiconductorprocess and

a second wafer in which the signal processing circuit decided as a goodproduct by electric inspection from among the signal processing circuitsformed by a semiconductor process is rearranged and embedded by theembedding member

are stacked by oxide film joining such that the wire between the firstsemiconductor element and the second semiconductor element iselectrically connected and then are singulated.

<25> An imaging apparatus including:

a backside illumination type solid-state imaging device that includes

-   -   a first semiconductor element including an imaging element        configured to generate a pixel signal in a unit of a pixel,    -   a second semiconductor element in which signal processing        circuits necessary for signal processing of the pixel signal are        embedded by an embedding member, and    -   a wire that electrically connects the first semiconductor        element and the second semiconductor element,    -   the first semiconductor element and the second semiconductor        element being stacked by oxide film joining.

<26> Electronic equipment including:

a backside illumination type solid-state imaging device that includes

-   -   a first semiconductor element including an imaging element        configured to generate a pixel signal in a unit of a pixel,    -   a second semiconductor element in which signal processing        circuits necessary for signal processing of the pixel signal are        embedded by an embedding member, and    -   a wire that electrically connects the first semiconductor        element and the second semiconductor element,    -   the first semiconductor element and the second semiconductor        element being stacked by oxide film joining.

REFERENCE SIGNS LIST

101 to 104 Wafer, 111 Solid-state imaging device, 120 Solid-stateimaging element, 120 a Terminal, 121 Memory circuit, 121 a, 121 a-1, 121a-2 Terminal, 122 Logic circuit, 122 a Terminal, 131 On-chip lens andon-chip color filter, 132 Support substrate, 133 Oxide film, 134, 134-1,134-2, 134A to 134H Wire, 135 Oxide film joining layer, 151Rearrangement substrate, 152 Adhesive, 161, 171 Support substrate, 321First semiconductor substrate, 322 Second semiconductor substrate, 323Third semiconductor substrate, 331 to 333 Multilayer wiring layer, 351,352, 361, 362, 372, 381, 382, 391, 401, 402 Contact, 441 Dummy circuit,441 a Dummy wire, 471 High thermal conductivity material member, 491Waterway, 495 Organic material member

What is claimed is: 1-26. (canceled)
 27. A light detecting devicecomprising: a first section including: a first semiconductor elementincluding a first semiconductor substrate at a light incident side and afirst multilayer wiring layer at a opposite side of the light incidentside; and a second section including: a second semiconductor elementincluding a second semiconductor substrate and a second multilayerwiring layer; and a third semiconductor element including a thirdsemiconductor substrate and a third multilayer wiring layer, wherein thefirst semiconductor element and the second semiconductor element arebonded together such that the first multilayer wiring layer and thesecond multilayer wiring layer face each other, wherein the firstsemiconductor element and the third semiconductor element are bondedtogether such that the first multilayer wiring layer and the thirdmultilayer wiring layer face each other, and wherein a size of the firstsemiconductor element is larger than a size of the second semiconductorelement.
 28. The light detecting device according to claim 27, whereinthe size of the first semiconductor element is larger than a size of thethird semiconductor element.
 29. The light detecting device according toclaim 27, wherein the size of the second semiconductor element is largerthan a size of the third semiconductor element.
 30. The light detectingdevice according to claim 27, wherein the first, second, and thirdmultilayer wiring layers include a plurality of pads, wherein theplurality of pads of the first and second multilayer wiring layers aredirectly bonded, and wherein the plurality of pads of the first andthird multilayer wiring layers are directly bonded.
 31. The lightdetecting device according to claim 30, wherein the plurality of padsare directly bonded with a CuCu connection.
 32. The light detectingdevice according to claim 27, wherein the second section furtherincludes an insulation film.
 33. The light detecting device according toclaim 32, wherein the second and the third semiconductor elements arecovered by the insulation film.
 34. The light detecting device accordingto claim 32, wherein the second semiconductor element other than abonding surface is covered by the insulation film.
 35. The lightdetecting device according to claim 32, wherein the third semiconductorelement other than a bonding surface is covered by the insulation film.36. The light detecting device according to claim 32, wherein at least aportion of the insulation film is disposed between the second and thethird semiconductor elements in a cross-sectional view.
 37. The lightdetecting device according to claim 27, wherein the first semiconductorsubstrate includes photoelectric conversion elements configured togenerate pixel signals.
 38. The light detecting device according toclaim 27, wherein the second semiconductor substrate includes a firstsignal process circuit configured to process pixel signals.
 39. Thelight detecting device according to claim 27, wherein the thirdsemiconductor substrate includes a second signal process circuitconfigured to process pixel signals.
 40. The light detecting deviceaccording to claim 27, wherein the second semiconductor substrateincludes a memory circuit.
 41. The light detecting device according toclaim 27, wherein the third semiconductor substrate includes a logiccircuit.
 42. An imaging apparatus comprising: a backside illuminationtype solid-state imaging device that includes: a first sectionincluding: a first semiconductor element including a first semiconductorsubstrate at a light incident side and a first multilayer wiring layerat a opposite side of the light incident side; and a second sectionincluding: a second semiconductor element including a secondsemiconductor substrate and a second multilayer wiring layer; and athird semiconductor element including a third semiconductor substrateand a third multilayer wiring layer, wherein the first semiconductorelement and the second semiconductor element are bonded together suchthat the first multilayer wiring layer and the second multilayer wiringlayer face each other, wherein the first semiconductor element and thethird semiconductor element are bonded together such that the firstmultilayer wiring layer and the third multilayer wiring layer face eachother, and wherein a size of the first semiconductor element is largerthan a size of the second semiconductor element.
 43. The imagingapparatus according to claim 42, wherein the first semiconductorsubstrate includes photoelectric conversion elements configured togenerate pixel signals.
 44. The imaging apparatus according to claim 42,wherein the second semiconductor substrate includes a memory circuit.45. The imaging apparatus according to claim 42, wherein the thirdsemiconductor substrate includes a logic circuit.
 46. The imagingapparatus according to claim 42, wherein the size of the firstsemiconductor element is larger than a size of the third semiconductorelement, and wherein the size of the second semiconductor element islarger than the size of the third semiconductor element.